ADP1074ACCZ-R7 datasheet(22/32 Pages) AD

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ADP1074

Data Sheet

Rev. D | Page 22 of 32

SYNCHRONOUS RECTIFIER (SR) DRIVERS

There are two synchronous rectifier drivers on the secondary

side for driving the synchronous switches. SR1 is the forward

driver that is in phase with the primary side NGATE driver,

and SR2 is the freewheeling driver. VDD2 is the front end of

the LDO at VREG2. The 5 V internal LDO at VREG2 powers

the SRx drivers and all internal circuits on the secondary side.

The recommended power supply range at VDD2 is from 6 V to

36 V. However, at 36 V input to VDD2, the power dissipation

in the LDO can be significant. If VDD2 is less than 5 V, the

LDO operates in the dropout region, where VREG2 and the

driver output are less than 5 V. In this case, it is recommended

to supply VDD2 with an auxiliary power supply greater than 5 V.

VDD2 can be directly connected to the converter output or an

auxiliary power supply, which can be realized by using a third

winding of the main transformer. For additional drive strength,

SR1 and SR2 can be fed into an external MOSFET driver such

as the ADP3624 or the ADP3654.

OUTPUT OVERVOLTAGE PROTECTION (OVP)

When the output voltage exceeds the OVP threshold of 1.36 V,

the controller immediately shuts off the drivers (NGATE, PGATE,

SR1, and SR2) on both the primary and secondary side. When

the voltage at the OVP drops below the OV hysteresis level, the

controller resumes switching in the next switching period with

the primary drivers, followed by phasing in of the SR1 and SR2

PWMs. The OVP feature causes the system to enter hiccup for

200 ms if the voltage on the OVP pin exceeds 1.36 V for a

sustained period of 200 μs.

ACTIVE CLAMP (PGATE)

In a forward converter, the magnetizing energy stored in the

transformer core during the on cycle must be demagnetized or

reset during the off cycle; otherwise, the transformer core

saturates in subsequent switching cycles. To reset the transformer

core, an active clamp switch is turned on during the off cycle,

which enables the reset of the transformer. This process reduces

power dissipation and increases overall efficiency. The active

clamp switch can be a high-side or a low-side switch using the

driver at the PGATE pin.

LEADING EDGE BLANKING

A leading edge blanking time is added after the rising edge of

the NGATE signal to avoid picking up any unwanted noise or

ringing at the CS pin at the start of the switching period.

GATE DELAY AND SR DEAD TIME

At high input voltages, the rise and fall times of the main MOSFET

on the primary side are larger than at lower input voltages. It is

important to have a programmable delay time between the PGATE

rising and the NGATE rising to account for different input

voltages, leakage inductances of the transformer, and MOSFET

output capacitances. Also, a sufficient gate delay between

PGATE and NGATE ensures zero volt switching (ZVS), which

is important for reducing switching losses in the main

MOSFET.

The total delay between the PGATE and NGATE rising edges

can be programmed with a resistor connected to the NGATE

pin. The resistor connected to NGATE is determined by the

ADP1074 prior to soft start. The programmable delay between

PGATE to NGATE has four discrete settings having typical

values of 30 ns, 60 ns, 100 ns, and 150 ns. See Figure 17 for

more details.

PGATE

FIXED

25ns

FIXED

25ns

30ns TO 150ns

SR DEAD TIME

(NGATE RESISTOR)

SR DEAD TIME

(NGATE RESISTOR)

SR2

SR1

NGATE

GATE DELAY

35ns

iCOUPLER DELAY

Figure 17. Gate Delay and SR Dead Time Settings

To maximize efficiency and avoid cross conduction between

the primary NGATE and SR2 (freewheeling switch), it is

necessary to have a delay time between SR2 and NGATE.

As shown in Figure 17, the NGATE falling edge and SR1 falling

edge turn off simultaneously with an iCoupler delay.

In addition, a dead time between SR1 and SR2 is internally

fixed to 25 ns (typical) to avoid shorting out the secondary

transformer winding.

LIGHT LOAD MODE (LLM) AND SR PHASE IN

Add a resistor at the MODE pin to enable the ADP1074 power

saving LLM feature. A current source from the MODE pin of

6.5 μA into this resistor sets up the LLM threshold voltage, which

is compared to the COMP voltage. When the COMP voltage

rises above the LLM threshold (that is, the MODE pin voltage),

the SRx PWMs gradually increase (or phase in) from the duty

cycle at light load to the steady state duty cycle at the SRx phase

in rate. The SRx phase in rate moves the SRx edges every

1.5 ns per μs. Without the phase in sequence, a dip in the output

voltage can occur if the SRx PWMs transition from zero to full

duty cycle instantaneously.

In a load dump situation, for example, when the load is stepped

from full load to light load, that is, from continuous conduction

mode (CCM) to discontinuous conduction mode (DCM) oper-

ation, the duty cycles of the SRx PWMs gradually phase out at

the SRx phase out rate, which has the same numerical value of

the SRx phase in rate. The phase out sequence of the SRx PWMs

prevents reverse current in the secondary, and at the same time,

optimizes the dynamic performance of the output response.

Note that the level of COMP is still above the minimum COMP

clamp level at this point, and the ADP1074 outputs duty cycles

with minimum on time.

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