ADP1074ACCZ-R7 datasheet(19/32 Pages) AD

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Data Sheet

ADP1074

Rev. D | Page 19 of 32

starts charging only when the primary current limit exceeds the

load current requirement.

The rate at which the SS1 pin voltage rises to the maximum

current limit is given by

dt = CSS1 × 1.5/(9.1 μA)

The handshaking process is as follows.

When VDD2 reaches the UVLO of approximately 3.5 V, the

internal circuitry on the secondary side is activated and the

ADP1074 initiates the following process:

The ADP1074 makes the voltage on the SS2 pin equal to

the value on the FB pin, with an SS2 pin current, at ten

times the nominal current source of 20 μA on the SS2 pin.

Simultaneously, the current limit on the primary (which is

the voltage on SS1) is transferred over to the secondary

side, and the voltage on the COMP pin is made equal to

the instantaneous SS1 voltage ± 100 mV. There is a

timeout for this process, which is 1.5 ms after the VDD2

UVLO threshold is crossed.

When this process is satisfied, the transmission of the COMP

signal occurs from the secondary to the primary side. The

ADP1074 transmits the COMP signal by continuously sampling

the analog signal at the COMP pin. The sampled value is then

transmitted using a proprietary scheme to the primary side where

the instantaneous value of the CS pin is compared to the COMP

level to determine the falling edge of the NGATE pulse. The

COMP signal is, therefore, a representation of the primary

current limit.

After COMP transmission begins, the primary side receives the

signal and control is completely handed over to the secondary

side when either the received level of COMP on the primary side

is within ±100 mV, or up to 128 switching periods (typically 8)

have passed, starting from the first pulse being transmitted to

the primary side.

Then, the control is handed over to the secondary side and the

closed-loop soft start begins, where the SS2 capacitor is charged

at a nominal rate of 20 μA. The output voltage then rises to the

regulation voltage based on the SS2 pin voltage. The voltage on

the SS2 pin continues to rise to 1.2 V, that is, the steady state

voltage on the FB pin. At this stage, the power supply is in

regulation, and the output voltage is at its target value.

At the end of the soft start process, the voltage on the SS2 pin

continues to rise to approximately 1.4 V. The instant that the

handover takes place, SS1 is discharged to 0 V. In steady state,

the FB pin (that is, the reference voltage) is 1.2 V.

The SR1 and SR2 synchronous drivers begin to pulse after

VDD2 crosses the UVLO threshold.

If the voltage at the VDD2 pin is greater than the UVLO voltage,

such as a soft start from the precharged output, or if the VDD2 pin

is powered by an external supply, the secondary side assumes

control from the moment the EN pin is enabled, and only SS2 is

used for the soft start procedure.

When initiating a soft start from the precharged output, the SS2

pin tracks the FB pin and then initiates a soft start. This process

eliminates any glitches in the output voltage.

When soft starting into a precharged output, the SRx gates are

prevented from turning on until the SS2 voltage has reached

the precharged voltage at the FB pin. This soft start scheme

prevents the output from being discharged, and it prevents reverse

current.

Under abnormal situations, such as a shorted load or a

transient condition on the load during the soft start process, FB

may not be able to track SS2 accurately. If this occurs before the

VDD2 UVLO threshold is crossed, SS1 is in control. If it occurs

after the VDD2 UVLO threshold is crossed, SS2 tracks the FB

pin and then continues with the soft start process until the

regulation voltage is reached. In all conditions, control is

handed over to the secondary if FB ≥ 1.2 V.

When the secondary VDD2 is directly powered by the output

of the converter, the minimum output voltage required is

higher than the secondary UVLO voltage. For output voltages

less than the secondary UVLO voltage, a third winding is needed

to generate an auxiliary voltage to power the secondary side

circuitry. Alternately, in most cases, a diode resistor capacitor

combination from the switch node can provide the voltage to

VDD2.

OUTPUT VOLTAGE SENSING AND FEEDBACK

The output voltage of the converter is set by a resistive divider

to the FB pin. The resistive divider must be set in a manner

such that the voltage at the FB pin is 1.2 V in steady state. The

output voltage must be differentially sensed using the FB pin

and the AGND2 pin.

LOOP COMPENSATION AND STEADY STATE

OPERATION

The FB pin feeds into the negative terminal of a transconductance

amplifier (or gm amplifier) with a gain of approximately 250 μA/V.

The positive input terminal of the gm amplifier is connected to SS2,

which provides the reference setpoint voltage. The output of

the gm amplifier is connected to the COMP pin. The voltage on

the COMP pin is representative of the current peak limit

required to sustain regulation. This pin is continuously

sampled, and the signal is transmitted to the primary side,

where it is compared to the sensed primary current using a

comparator. When the comparator trips, it causes NGATE to

terminate.

Typically, an RC network in series is connected between the

COMP pin and AGND2 for compensation. A high frequency pole

in the form of a capacitor can also be added in parallel to the RC

network.

The output of the gm amplifier is clamped to a minimum and

maximum current of approximately −57 μA and +43 μA,

respectively.

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