ADP1074ACCZ-R7 datasheet(21/32 Pages) AD

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Data Sheet

ADP1074

Rev. D | Page 21 of 32

R3 is sized to bias the Zener diode and R4 is sized such that

(VZENER – 1)/R4 > IZENER, where VZENER is the voltage of the

diode and IZENER is the biasing current of the diode. This

sizing ensures that the impedance of the resistor is less

than the impedance of the diode, which causes the voltage

of the diode to drop, and allows VDD2 to enter UVLO.

If the output voltage is <5 V, the same procedure can be

used to size the R4 resistor. If a discrete LDO is not used, a

simple resistor and diode connector to the output voltage

is sufficient. In this case, the R4 resistor is sized to limit the

current through the D1 diode when the output voltage is

0 V during a short-circuit event. Because the bandwidth of

the system is high, the ADP1074 is able to maintain

voltage regulation at the proper voltage level, even if the

auxiliary winding voltage is higher than the output voltage.

The soft start and soft start from precharge conditions is

met with the addition of this circuit due to the bandwidth

of the overall system.

500Ω

100Ω

VDD2

VOUT

AGND2

~6.3V

ZENER

VOUT

100Ω

ALTERNATE OPTION

FROM AUMILIARY

WINDING

~10V

Figure 15. Recommended Circuit to Guarantee Hiccup Mode Showing

Typical Values

TEMPERATURE SENSING

The ADP1074 has an internal temperature sensor that shuts

down the controller when the internal temperature exceeds the

OTP limit. At this time, the primary and secondary MOSFET

drivers (PGATE, NGATE, SR1, and SR2) are held low. When the

temperature drops below the OTP hysteresis level, the ADP1074

restarts with a soft start sequence.

FREQUENCY SETTING (RT PIN)

The switching frequency can be programmed in a range of

50 kHz to 600 kHz by connecting a resistor from RT to AGND1.

A small current flows out of the RT pin and the voltage across it

sets up the internal oscillator frequency. The value of this pin is

approximately 1.224 V in steady state. Use the following equation

to determine the resistor (in Ω) for a particular switching

frequency (in kHz):

1000

)

(

(kHz)











BOT

TOP

where:

fS is the switching frequency.

RTOP is the top resistor of the divider.

RBOT is the bottom resistor of the divider.

MAXIMUM DUTY CYCLE

To prevent the transformer core from saturating in the event of

high current or extreme load transient and reduce voltage stress

on the MOSFETs, a maximum duty cycle clamp can be set by

connecting the DMAX pin to the center tap of the resistive

divider that is connected from RT to AGND1, as shown in

Figure 16.

RTOP

RBOT

DMAX

ADP1074

PGND1

AGND1

Figure 16. Setting the Maximum Duty Cycle, DMAX

The maximum duty cycle is calculated by the following:

)

(

BOT

TOP

BOT

MAX









where:

DMAX is 50% when RBOT is 0 Ω or when the DMAX pin is

connected to AGND1. For example, when RTOP is equal to RBOT,

DMAX is 75%. DMAX can reach 100% if RTOP is 0 or when RBOT

becomes open circuit.

RBOT is the bottom resistor of the divider.

RTOP is the top resistor of the divider.

As an added protection feature to prevent open-loop conditions,

the maximum duty cycle is also applicable during soft start. If the

controller reaches DMAX during soft start for three con-

secutive switching periods, the 40 ms hiccup timer is initiated.

FREQUENCY SYNCHRONIZATION

The switching frequency of the ADP1074 can be synchronized

to an external clock at the SYNC pin. When an external clock

rising edge is first detected, it takes approximately seven to ten

periods for the internal clock to lock in the SYNC clock frequency.

In between the time that the SYNC clock is detected and the

time that it is locked in, the controller continues to operate with

the internal oscillator frequency.

The SYNC frequency must be within ±10% of the internal

oscillator frequency set by the RT pin; otherwise, synchronization

does not take place.

A clock signal can be applied to SYNC on the fly or prior to the

soft start sequence. A dithered clock can also be applied to

SYNC to reduce the peak electromagnetic interference (EMI)

noise in the converter output and switch node. The internal

clock is able to lock onto the dithered clock cycle by cycle.

It is recommended to connect the SYNC pin to AGND1 if this

feature is not used.

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