ZSC31015EEG1-R datasheet(33/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

3.5.

EEPROM Bits

Table 3.5 shows the bit order and default settings for the EEPROM, which are programmed through the serial

interface. See section 5 for important information for die/wafer customers.

Table 3.5

ZSC31015 EEPROM Bits

EEPROM

Range

Description

Default

Settings

As of ww08/2009

Notes

2:0

Osc_Trim

0HEX

This default setting

minimizes risk of

communication

failure on start-up.

(Actual part-specific

factory values for

Osc_Trim are

initially stored in bits

in CUST_ID1 and

CUST_ID2 for appli-

cations requiring op-

timal response time.

See section 5 for

important notes.)

See section 2.5 for details on oscillator trim.

100 => Fastest

101 => 3 clicks faster than nominal

110 => 2 clicks faster than nominal

111 => 1 click faster than nominal

000 => Nominal

001 => 1 click slower than nominal

010 => 2 clicks slower than nominal

011 => Slowest

6:3

1V_Trim/JFET_Trim

ssssBIN

where “s” is the part-

specific factory bit

setting for the

reference voltage

trim value.

(Back-up copies are

stored in CUST_ID0

for applications re-

quiring accurate

references. See

section 5 for impor-

tant notes.)

See Table 2.1

in the “Voltage Reference Block” section.

10:7

A2D_Offset

3HEX

The upper two bits are flip polarity and invert bridge input

(negative gain) respectively. If both are used in conjunction,

negative offset modes can be achieved.

00 => normal polarity, positive gain

01 => normal polarity, negative gain

10 => flip polarity, positive gain

11 => flip polarity, negative gain

The lower two bits form the ADC offset selection.

Offset selection:

11 => [-1/2,1/2] mode bridge inputs

10 => [-1/4,3/4] mode bridge inputs

01 => [-1/8,7/8] mode bridge inputs

00 => [-1/16,15/16] mode bridge inputs

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