ZSC31015EEG1-R datasheet(25/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

Bit Window

104.2µsec @ 9.6 kHz baud

40 µsec @ 26kHz baud

Start Bit

Logic 1

Logic 0

3.2.

ZACwire™ Communication Interface

3.2.1.

Properties and Parameters

Table 3.1

Pin Configuration and Latch-Up Conditions

No.

Parameter

Symbol

Min

Typ

Max

Unit

Comments

Pull-up resistor (on-chip)

RZAC,pu

Ω

On-chip pull-up resistor switched on

during Digital Output Mode and during

CM Mode (first 3 ms after power up).

Pull-up resistor (external)

RZAC,pu_ext

150

Ω

If the master communicates via a push-

pull stage, no pull-up resistor is needed;

otherwise, a pull-up resistor with a value

of at least 150

Ω must be connected.

ZACwire™ rise time

tZAC,rise

µs

Any user RC network included in the

Sig™ path must meet this rise time.

ZACwire™ line resistance

RZACload

3.9

Ω

Also see section 1.3.8.

ZACwire™ load capacitance

CZAC,load

Also see section 1.3.8.

Voltage low level

VZAC,low

0.2

VDD

Rail-to-rail CMOS driver.

Voltage high level

VZAC,high

0.8

VDD

Rail-to-rail CMOS driver.

The rise time must be tZAC,rise = 2  RZACload  CZACload  5 s . If using a pull-up resistor instead of a line resistor, it must meet this

specification. The absolute maximum for CZACload is 15nF.

3.2.2. Bit Encoding

Figure 3.2

Manchester Duty Cycle

Start bit = 50% duty cycle used to set up strobe time

Logic 1 = 75% duty cycle

Logic 0 = 25% duty cycle

Stop Time

The ZACWire™ bus will be held high for 32μs (nominal)

between consecutive data packets regardless of baud rate.

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