ZSC31015EEG1-R datasheet(18/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

Settling Time

s

AD Conversion

768

s

Calculation

160

s

DAC output

occurs here

DAC output

next update

Settling Time

s

AD Conversion

768

s

Calculation

160

s

Example for the upper clipping level: If the Up_Clip_Lim[6:0] = 0000000, then the 14-bit value used for the

clipping threshold is 11000000011111. This is 75.19% of full scale. Since there are 7 bits of upper clipping limit,

there are 127 possible values between 75.19% and 100%. Therefore the resolution of the clipping limits 0.195%.

Example for the lower clipping level: If the Low_Clip_Lim[6:0] = 1111111, then the 14-bit value used for the

clipping threshold is 00111111100000. This is 24.8% of full scale. Since there are 7 bits of lower clipping limit,

there are 127 possible values between 0 and 24.8%. Therefore the resolution of the lower clipping limit is 0.195%.

Figure 2.2 shows the data timing of the DAC output for the update rate setting 00.

Figure 2.2

DAC Output Timing for Highest Update Rate

2.4.2.

Output Buffer

A rail-to-rail op amp configured as a unity gain buffer can drive resistive loads (whether pull-up or pull-down) as

low as 5k

 and capacitances up to 15nF (for pure analog output). In addition, to limit the error due to amplifier

offset voltage, an error compensation circuit is included which tracks and reduces offset voltage to < 1mV. The

output of the ZSC31015 output can be permanently shorted to VDD or VSS without damaging the device. The

output driver contains a current-limiting block that detects a hard short and limits the current to a safe level. The

short circuit protection current can vary from a minimum of 3mA to a maximum of 40mA depending on operating

conditions. Output short circuit protection can be enabled via Diag_cfg (EEPROM [102:100]). Enabling this

protection is recommended when using the analog output.

2.4.3.

Voltage Reference Block

A linear regulator control circuit is included in the Voltage Reference Block to interface with an external JFET to

allow operation in systems where the supply voltage exceeds 5.5V. This circuit can also be used for over-voltage

protection. The regulator set point has a coarse adjustment controlled by the JFET_cfg EEPROM bits that can

adjust the set point around 5.0 or 5.5V. (See Table 3.5 for bit locations and section 2.3.1 regarding writing to the

EEPROM.). The 1V trim setting (see below) can also act as a fine adjust for the regulation set point. The 5V

reference can be trimmed within +/-15mV.

Note: If using the external JFET for over-voltage protection purposes (i.e., 5V at JFET drain and expecting 5V at

JFET source), there will be a voltage drop across the JFET; therefore ratiometricity will be slightly compromised

depending on the rds(on) of the chosen JFET. A Vishay J107 is the best choice because it has only an 8mV drop

worst case. If using as regulation instead of over-voltage protection, a MMBF4392 or BSS169 also works well.

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