ZSC31015EEG1-R datasheet(26/53 Pages) RENESAS

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November 14, 2016

ZSC31015 Datasheet

3.2.3.

Write Operation from Master to ZSC31015

The calibration master sends a 19-bit packet frame to the IC.

Figure 3.3

19-Bit Write Frame

The incoming serial signal will be sampled at a 512 kHz clock rate. This protocol is very tolerant to clock skew,

and can easily tolerate baud rates in the 6 kHz to 48 kHz range.

3.2.4.

ZSC31015 Read Operations

The incoming frame will be checked for proper parity on both, command and data bytes, as well as for any edge

time-outs prior to a full frame being received.

Once a command/data pair is received, the ZSC31015 will perform that command. After the command has been

successfully executed by the ZSC31015, it will acknowledge success by a transmission of an A5HEX-byte back to

the master. If the master does not receive an A5HEX transmission within 130 ms of issuing the command, it must

assume the command was either improperly received or could not be executed.

Figure 3.4

Read Acknowledge

5 4 3 2 1 0

Command Byte

Data Byte

Start Bit

Parity Bit of Command or Data Byte

Command Bit (example: Bit 2)

7 6

5 4 3 2 1 0

7 6

Data Bit (example: Bit 2)

19-bit Frame (WRITE)

Data Byte

Start Bit

Parity Bit of Data Byte

Data Bit (Low)

1 0 0 1 0 1

1 0

Data Bit (High)

1 DATA Byte Packet

(10-bit byte A5

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