AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 32 of 39

CS MODE, 3-WIRE WITH THE BUSY INDICATOR

This mode is typically used when a single AD4020/AD4021/

AD4022 device is connected to an SPI-compatible digital host

with an interrupt input (IRQ). The connection diagram is

shown in Figure 57, and the corresponding timing diagram is

shown in Figure 58.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable bit in the configuration

register to 0 (see Table 12). Turbo mode is disabled by default.

When performing conversions in this mode, SDI must be held

high. SDI can be connected to VIO if register reading and writing

is not required. A rising edge on CNV initiates a conversion and

forces SDO to high impedance. SDO remains high impedance

until the completion of the conversion, irrespective of the state of

CNV. Prior to the minimum conversion time, CNV can select

other SPI devices, such as analog multiplexers. However, CNV

must be returned low before the minimum conversion time

conversion time to guarantee generating the busy signal indicator.

When the conversion is complete, the AD4020/AD4021/AD4022

then enter the acquisition phase and power down. There must not

be any digital activity on the SCK during the conversion.

When the conversion is complete, SDO is driven low. With a

pull-up resistor (for example, 1 kΩ) on the SDO line, this

transition can be used as an interrupt signal to initiate the data

reading controlled by the digital host. The data bits are then

clocked out MSB first on SDO by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate, provided it has an acceptable hold

clocked out on SDO on the first 20 SCK falling edges. If the status

returns to high impedance after an optional additional SCK

falling edge or the next CNV rising edge (whichever occurs first).

If multiple AD4020/AD4021/AD4022 devices are selected at the

same time, the SDO output pin handles this contention without

damage or induced latch-up. It is recommended to keep this

contention as short as possible to limit extra power dissipation.

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

IRQ

VIO

1kΩ

AD4020/

AD4021/

AD4022

TO WRITE TO THE CONFIGURATION REGISTER.

Figure 57. CS Mode, 3-Wire with Busy Indicator Connection Diagram

SDO

D19

D18

D1

D0

SCK

12

3

19

20

21

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

Figure 58. CS Mode, 3-Wire with the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)