AD4022BCPZ-R2 datasheet(19/39 Pages) AD

19 / 39 page

Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 19 of 39

CONVERTER OPERATION

The AD4020/AD4021/AD4022 are SAR-based ADCs using a

charge redistribution sampling digital-to-analog converter

(DAC). Figure 38 shows the simplified schematic of the ADC. The

capacitive DAC consists of two identical arrays of 20 binary

weighted capacitors that are connected to the comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to the GND pin via the

SW+ and SW− switches (see Figure 38). All independent

switches connect the other terminal of each capacitor to the

analog inputs. The capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs.

When the acquisition phase is complete and the CNV input

goes high, a conversion phase initiates. When the conversion

phase begins, SW+ and SW− are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the GND input. The differential voltage between the IN+ and IN−

inputs captured at the end of the acquisition phase is applied to the

comparator inputs, unbalancing the comparator. By switching

each element of the capacitor array between the GND pin and

VREF, the comparator input varies by binary weighted voltage

steps (VREF/2, VREF/4, …, VREF/1,048,576). The control logic toggles

these switches, starting with the MSB, to bring the comparator

back into a balanced condition. After the process completes, the

control logic generates the ADC output code and a busy signal

indicator.

Because the AD4020/AD4021/AD4022 have on-board conversion

clocks, the serial clock, SCK, is not required for the conversion

process.

TRANSFER FUNCTIONS

The ideal transfer characteristics for the AD4020/AD4021/

AD4022 are shown in Figure 39 and Table 9.

100...000

100...001

100...010

011...101

011...110

011...111

ANALOG INPUT

+FSR – 1.5 LSB

+FSR – 1 LSB

–FSR + 1 LSB

–FSR

–FSR + 0.5 LSB

Figure 39. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 9. Output Codes and Ideal Input Voltages

Description

Analog Input, VREF = 5 V

VREF = 5 V with Span Compression Enabled

Digital Output Code (Hex)

FSR − 1 LSB

+4.99999046 V

+3.99999237 V

0x7FFFF1

Midscale + 1 LSB

+9.54 µV

+7.63 µV

0x00001

Midscale

0 V

0x00000

Midscale − 1 LSB

−9.54 µV

−7.63 µV

0xFFFFF

−FSR + 1 LSB

−4.99999046 V

−3.99999237 V

0x80001

−FSR

−5 V

−4 V

0x800002

This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.8 × VREF with span compression

enabled).

This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with span compression disabled and below -0.8 × VREF with span compression

enabled).

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