ADIS16486

Data Sheet

Rev. 0 | Page 4 of 38

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Input Current

10

µA

All Pins Except RST

10

µA

RST Pin

0.33

mA

10

pF

DIGITAL OUTPUTS

Output Voltage

2.4

V

0.4

V

FLASH MEMORY

100,000

Cycles

20

Years

Time until data is available

Power-On Start-Up Time

600

ms

Backup

1370

1500

ms

390

600

ms

Sleep Mode Recovery Time

730

1000

µs

Flash Memory

1.05

6.8

sec

Test Time

50

ms

On Demand Self Test (ODST) Time

Using internal clock (2460 Hz)

12

ms

CONVERSION RATE

2.46

kSPS

Initial Clock Accuracy

0.02

%

Temperature Coefficient

40

ppm/°C

Sync Input Clock

2.4

kHz

POWER SUPPLY

VDD

Operating voltage range

3.0

3.6

V

Normal mode, µ + 1 σ

186

mA

Sleep mode

12.2

mA

Power-down mode

37

µA

Operating voltage range

3.0

3.3

3.6

V

Real-Time Clock (RTC) Supply

Current

Normal mode, VDDRTC = 3.3 V

13

µA

1

The repeatability specifications represent analytical projections based on the following drift contributions and conditions: temperature hysteresis (−40°C to +85°C),

electronics drift (high temperature operating life test: +110°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles, −55°C to +85°C), rate

random walk (10-year projection), and broadband noise.

2

Bias repeatability describes a long-term behavior over a variety of conditions. Short-term repeatability relates to the in-run bias stability and noise density specifications.

3

All specifications associated with the accelerometers relate to the full-scale range of ±18 g.

4

X-ray exposure can degrade this performance metric.

5

The digital input and output signals use a 3.3 V system.

6

Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.

7

8

These times do not include thermal settling and internal filter response times, which may affect overall accuracy.

9

The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.

10

Monitoring the data ready signal (see Table 143 for the FNCTIO_CTRL register configuration) for the return of regular pulsing can help minimize system wait times.

11

The device functions at clock rates below 0.7 kHz, but at reduced performance levels.

12

Supply current transients can reach 600 mA during initial startup or reset recovery.

13

Connecting the VDDRTC supply is a requirement, even if the application does not use the RTC function.