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Data Sheet

ADPA7007

Rev. 0 | Page 17 of 23

APPLICATIONS INFORMATION

Figure 55 shows the basic connections for operating the

ADPA7007. All measurements for this device were taken using

the typical application circuit shown in Figure 55.

Capacitive bypassing is required for all VGGx and VDDx pins. VGG1

and VGG2 are the gate bias pins, and VDD1 to VDD6 are the drain

bias pins for the cascaded amplifier.

The power supply and gate voltage decoupling capacitors

shown in Figure 55 represent the configuration that was used to

characterize and qualify the device. There may be scopes to

reduce the number of capacitors, but scopes vary from system

to system. It is recommended to first remove or combine the

largest capacitors that are farthest from the device. The

following is the recommended bias sequence during power-up:

1. Connect the power supply ground to circuit ground (GND).

2. Set the gate bias voltages, VGG1 and VGG2, to −1.5 V.

3. Set all drain bias voltages (VDDx) to 5 V.

4. Increase the gate bias voltage to achieve the quiescent

supply current and set IDQ = 1400 mA.

5. Apply the RF signal.

The following is the recommended bias sequence during

power-down:

1. Turn off the RF signal.

2. Decrease the gate bias voltages, VGG1 and VGG2, to −1.5 V to

achieve an IDQ = 0 mA (approximately).

3. Decrease all drain bias voltages to 0 V.

4. Increase the VGGx gate bias voltage to 0 V.

The VDD = 5 V and IDQ = 1400 mA bias conditions are recom-

mended to optimize overall performance when the gate voltage

is being held at a fixed value (note that with the gate voltage held at

a fixed value, the drain current, IDD, increases as the RF input

power level is increased, as shown in Figure 41). Unless otherwise

noted, the data shown was taken using the recommended bias

conditions. Operation of the ADPA7007 at different bias

conditions can result in different performance. Biasing the

ADPA7007 for higher quiescent drain current typically results

in higher gain and output P1dB at the expense of increased

power dissipation (see Table 8).

Table 8. Power Selection1,2

IDQ (mA)

Gain (dB)

Output P1dB (dBm)

Output IP3 (dBm)

PDISS (W)

VGGx (V)

1200

15.80

31.89

42.90

−0.73

1400

16.20

31.93

41.30

−0.68

1600

16.50

31.95

39.55

−0.63

Data taken at the following nominal bias conditions: VDD = 5 V, TA = 25°C, frequency = 32 GHz.

Adjust VGG1 and VGG2 from −1.5 V to 0 V to achieve the desired quiescent drain current, IDQ.

C31

4.7µF

C26

1000pF

C21

100pF

C16

4.7µF

C10

1000pF

100pF

C17

4.7µF

C11

1000pF

100pF

C15

4.7µF

1000pF

100pF

1000pF

C14

4.7µF

100pF

1000pF

C13

4.7µF

100pF

C12

1000pF

C18

4.7µF

C23

100pF

C19

1000pF

C30

4.7µF

RFOUT

RFIN

VDET

VREF

ADPA7007

VGG1

VGG2

VDD1,

VDD3,

VDD5

+5V

–5V

VDD2,

VDD4,

VDD6

–

100kΩ

10kΩ

VOUT = VREF – VDET

10kΩ

SUGGESTED CIRCUIT

Figure 55. Typical Application Circuit

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