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FXLS8967AF 数据表(PDF) 49 Page - NXP Semiconductors

部件名 FXLS8967AF
功能描述  3-Axis Low-g Accelerometer
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FXLS8967AF 数据表(HTML) 49 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8967AF
3-Axis Low-g Accelerometer
ODR[3]
ODR[2]
ODR[1]
ODR[0]
ODR
selection
(Hz)
Decimation
selection
(samples)
Noise RMS (mg)[1][2]
IDD
(µA)
1
1
1
1
0.781
4096
0.29
150
Table 53. WAKE and SLEEP High Performance mode ODR and decimation settings...continued
[1]
Values are for ±2 g FSR only.
[2]
Based on post board mount characterization data. Tested on a mechanically isolated granite table to provide isolation from environmental vibration.
DEC[3]
DEC[2]
DEC[1]
DEC[0]
Decimation selection
(samples)
Measurement time
(ms)
0
0
0
0
1
0.3125
0
0
0
1
2
0.625
0
0
1
0
4
1.25
0
0
1
1
8
2.5
0
1
0
0
16
5
0
1
0
1
32
10
0
1
1
0
64
20
0
1
1
1
128
40
1
0
0
0
256
80
1
0
0
1
512
160
1
0
1
0
1024
320
1
0
1
1
2048
640
1
1
0
0
4096
1280
1
1
0
1
4096
1280
1
1
1
0
4096
1280
1
1
1
1
4096
1280
Table 54. WAKE and SLEEP decimation settings in Flexible Power mode
15.14 SENS_CONFIG4 register (address 18h)
Bit
7
6
5
4
3
2
1
0
Name
EXT_
TRIG_M
WAKE_
SDCD_WT
WAKE_
SDCD_OT
WAKE_
ORIENT
DRDY_PUL INT2_FUNC
INT_
PP_OD
INT_POL
Reset
0
0
0
0
0
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 55. SENS_CONFIG4 register (address 18h) bit allocation
FXLS8967AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Objective data sheet
Rev. 1 — 27 April 2021
49 / 98



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