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FXLS8967AF 数据表(PDF) 60 Page - NXP Semiconductors

部件名 FXLS8967AF
功能描述  3-Axis Low-g Accelerometer
PDF  98 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FXLS8967AF 数据表(HTML) 60 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8967AF
3-Axis Low-g Accelerometer
For example, writing the value +16 (10h) into the OFF_X register in the ±4 g FSR results
in an effective X-axis offset of 16 LSB * 2 * 1.95 mg/LSB = 62.4 mg.
Bit
7
6
5
4
3
2
1
0
Name
OFF_X[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 75. OFF_X register (addresses 22h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
OFF_Y[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 76. OFF_Y register (addresses 23h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
OFF_Z[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 77. OFF_Z register (addresses 24h) bit allocation
15.24 BUF_CONFIG1 register (address 26h)
The BUF_CONFIG1 register controls the output buffer read order, data collection mode
and trigger event sources.
Bit
7
6
5
4
3
2
1
0
Name
BUF_TYPE
BUF_MODE[1:0]
BUF_GATE
TRIG_
SDCD_WT
TRIG_
SDCD_OT
—
TRIG_
ORIENT
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 78. BUF_CONFIG1 register (address 26h) bit allocation
Field
Description
7
BUF_TYPE
Buffer data read out order:
0: First In First Out (FIFO). Default
In FIFO mode, the oldest sample data is read out first, followed by the more recent sample data.
1: First In Last Out (LIFO).
In LIFO mode, the newest data sample is read out first, followed by the older sample data.
Note: It is not possible to change the buffer operating mode without first clearing the SENS_
CONFIG1[ACTIVE] and SENS_CONFIG4[INT2_FUNC] bits.
Table 79. BUF_CONFIG1 register (address 26h) bit description
FXLS8967AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Objective data sheet
Rev. 1 — 27 April 2021
60 / 98



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