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FXLS8967AF 数据表(PDF) 13 Page - NXP Semiconductors |
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FXLS8967AF 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 98 page  NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer I2C Standard- mode[1] I2C Fast-mode[1] I2C Fast-mode Plus[2] Parameter Symbol Min Max Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 0 1000 kHz Bus free time between STOP and START conditions tBUF 4.7 — 1.3 — 0.5 — µs Repeated START hold time tHD;STA 4 — 0.6 — 0.26 — µs Repeated START setup time tSU;STA 4.7 — 0.6 — 0.26 — µs STOP condition setup time tSU;STO 4 — 0.6 — 0.26 — µs SDA valid time[3] tVD;DAT — 3.45[4] — 0.9[4] — 0.45[4] µs SDA valid acknowledge time[5] tVD;ACK — 3.45[4] — 0.9[4] — 0.45[4] µs SDA setup time tSU;DAT 250 — 100[6] — 50 — ns SCL clock low time tLOW 4.7 — 1.3 — 0.50 — µs SCL clock high time tHIGH 4.0 — 0.6 — 0.26 — µs SDA and SCL risetime tr — 1000 20 300 — 120 ns SDA and SCL fall time[7][8] tf — 300 20*(VDD/5.5) 300 20*(VDD/5.5) 120 ns Pulse width of spikes on SDA and SCL (suppressed by the input filter) tSP 0 50 0 50 0 50 ns Table 12. I2C secondary timing values for Standard-mode (Sm), Fast-mode (Fm), and Fast-mode Plus (Fm +) [1] All values referred to VIH(min) and VIL(max) levels. [2] Should be backward compatible with Fast mode. [3] tVD;DAT referred to the time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). [4] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode respectively, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. [5] tVD;ACK = time for ACK signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). [6] A Fast-mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. Also the acknowledge timing must meet this set-up time. [7] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. The maximum fall time allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [8] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this specified fall time when considering bus timing. FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 13 / 98 |
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