PCF8553DTTSLASHA datasheet(4/51 Pages) NXP

4 / 51 page

NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol

Type

Description

SEG34 to SEG39 1 to 6

SEG0 to SEG33

23 to 56

output

LCD segments

COM0 to COM3

7 to 10

output

LCD backplanes

Supply pins

VLCD

supply

LCD supply voltage

VDD

supply

supply voltage

VSS

supply

ground supply

Clock and control pins

RST

input

reset input, active LOW

PORE[1]

input

Power-On Reset (POR) enable

• connect to VDD for enabling POR

• connect to VSS (or leave open) for disabling POR

CLK

input/output internal oscillator output, external oscillator input

• must be left open if unused

Bus-related pins

I2C-bus

SPI-bus

interface selector input

IFS[1]

input

• connect to VSS (or leave open)

• connect to VDD

SDIO

input/output unused

serial data input/output

A0[1]

input

A1[1]

input

hardware device address selection;

• connect to VSS (or leave open) for

logic 0

• connect to VDD for logic 1

unused

SCL

input

serial clock input

SDA/CE

input/output serial data output

chip enable input, active LOW

Table 3. Pin description of PCF8553DTT (TSSOP56)...continued

[1]

A series resistance between VDD and the pin must not exceed 1 kΩ to ensure proper functionality, see Section 15.3.

7 Functional description

7.1 Registers of the PCF8553

The registers of the PCF8553 are arranged in bytes with 8 bit, addressed by an address

pointer. Table 4 depicts the layout.

Bits labeled as 0 must always be written with logic 0.

Address Bits

AP[4:0]

Reference

Command registers

Table 4. Registers of the PCF8553

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

4 / 51

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