PCF8553DTTSLASHA datasheet(8/51 Pages) NXP

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NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

Bit

Symbol

Value

Description

blinking on, fblink = 1 Hz

blinking on, fblink = 2 Hz

inversion mode selection

0[1]

line inversion (driving scheme A)

INV

frame inversion (driving scheme B)

Table 7. Display_ctrl_2 - display control command 2 register (address 03h) bit

description...continued

[1]

Default value.

7.2.3.1 Blinking

The whole display blinks at frequencies selected by the blink control bits BL[1:0], see

Table 7. The blink frequencies are derived from the clock frequency. During the blank-out

phase of the blinking period, the display is turned off.

If an external clock with frequency fclk(ext) is used, the blinking frequency is determined by

Equation 1. For notation, see Section 8.2.

(1)

7.2.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)

The waveforms used to drive LCD inherently produce a DC voltage across the display

cell. The PCF8553 compensates for the DC voltage by inverting the waveforms on

alternate frames or alternate lines. The choice of compensation method is determined

with the INV bit.

7.3 Starting and resetting the PCF8553

If the internal Power-On Reset (POR) is enabled by connecting pin PORE to VDD, the

chip resets automatically when VDD rises above the minimum supply voltage. No further

action is required.

If the internal POR is disabled by connecting pin PORE to VSS, the chip must be reset

by driving the RST pin to logic 0 for at least 10 μs, see Figure 4. See also application

information in Section 15.

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

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