IMX6SDLCEC datasheet(8/169 Pages) NXP

8 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Introduction

— Four Pulse Width Modulators (PWM)

— System JTAG Controller (SJC)

— GPIO with interrupt capabilities

— 8x8 Key Pad Port (KPP)

— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx

— Two Controller Area Network (FlexCAN), 1 Mbps each

— Two Watchdog timers (WDOG)

— Audio MUX (AUDMUX)

— MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50, MOST150)

with the option of DTCP cipher accelerator

The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers:

•

Provide PMU, including LDO supplies, for on-chip resources

•

Use Temperature Sensor for monitoring the die temperature

•

Support DVFS techniques for low power modes

•

Use SW State Retention and Power Gating for Arm and MPE

•

Support various levels of system power modes

•

Use flexible clock gating control scheme

The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted

multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance

at low power consumption numbers, while having the CPU core relatively free for performing other tasks.

The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators:

•

VPU—Video Processing Unit

•

IPUv3H—Image Processing Unit version 3H

•

GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5

•

GPU2Dv2—2D Graphics Processing Unit (BitBlt)

•

PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to

support the EPD display applications.

•

ASRC—Asynchronous Sample Rate Converter

Security functions are enabled and accelerated by the following hardware:

•

Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)

•

SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking

the access to the system debug features.

•

CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash

engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).

•

SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock

•

CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be

configured during boot and by eFUSEs and will determine the security level operation mode as

well as the TZ policy.

IMX6SDLCEC 数据表(PDF) 8 Page - NXP Semiconductors

IMX6SDLCEC 数据表(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载