IMX6SDLCEC datasheet(98/169 Pages) NXP

98 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

NOTE

Table 66 provides information for both the DISP0 and DISP1 ports.

However, DISP1 port has reduced pinout depending on IOMUXC

configuration and therefore may not support all the above configurations.

See the IOMUXC chapter of the i.MX 6Solo/6DualLite Reference Manual

(IMX6SDLRM).

4.11.10.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

DIx_PIN4

—

Additional frame/row synchronous

signals with programmable timing

DIx_PIN5

—

DIx_PIN6

—

DIx_PIN7

—

DIx_PIN8

—

DIx_D0_CS

—

DIx_D1_CS

—

Alternate mode of PWM output for

contrast or brightness control

DIx_PIN11

—

DIx_PIN12

—

DIx_PIN13

—

DIx_PIN14

—

Optional RS2

DIx_PIN15

DRDY/DV

Data validation/blank, data enable

DIx_PIN16

—

Additional data synchronous

signals with programmable

features/timing

DIx_PIN17

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

• A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.

• The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.

3 This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

Table 66. Video Signal Cross-Reference (continued)

i.MX 6Solo/6DualLite

LCD

Comment1,2

Port Name

(x=0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb3

16-bit

YCrCb

20-bit

YCrCb

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