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ADUCM3029BCBZ-R7 数据表(PDF) 24 Page - Analog Devices

部件名 ADUCM3029BCBZ-R7
功能描述  Ultra Low Power Arm Cortex-M3 MCU with Integrated Power Management
PDF  39 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADUCM3029BCBZ-R7 数据表(HTML) 24 Page - Analog Devices

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ADuCM3027/ADuCM3029
Data Sheet
Rev. B | Page 24 of 39
RESERVED
REAL-TIME CLOCK 0 (RTC 0)
0x4000 1044
0x4000 1000
RESERVED
GENERAL-PURPOSE TIMER 2
0x4000 0824
0x4000 0800
RESERVED
INSTRUCTION SRAM (32kB)
0x1000 7FFF
0x1000 0000
RESERVED
256kB FLASH MEMORY
0x0003 FFFC
0x0000 0000
RESERVED
GENERAL-PURPOSE TIMER 1
0x4000 0424
0x4000 0400
RESERVED
GENERAL-PURPOSE TIMER 0
0x4000 0424
0x4000 0400
RESERVED
RAM BANK 1 (16kB)
0x2004 3FFF
0x2004 0000
RESERVED
0x2000 3FFF
0x2000 0000
RAM BANK 0 (16kB)
DMA0
0x4001 0FE0
0x4001 0000
BEEPER 0
0x4000 5C0C
0x4000 5C00
RESERVED
UART 0
0x4000 5030
0x4000 5000
RESERVED
RESERVED
ADC0
0x4000 70C4
0x4000 7000
RESERVED
SPI 1 MASTER/SLAVE
0x4000 4438
0x4000 4400
0x4000 4038
0x4000 4000
RESERVED
SPI 0 MASTER/SLAVE
RESERVED
I2C 0 MASTER/SLAVE
0x4000 3058
0x4000 3000
RESERVED
WATCHDOG TIMER
0x4000 2C18
0x4000 2C00
RESERVED
SYSTEM ID AND DEBUG
ENABLE
0x4000 2040
0x4000 2000
0x4000 1444
0x4000 1400
RESERVED
REAL-TIME CLOCK 1 (RTC1)
RESERVED
POWER MGT, EXT IRQ,
CLOCKING, MISC MMR
0x4004 C80C
0x400F FFFF
0x4004 C000
RESERVED
CRYPTO
0x4004 406C
0x4004 4000
RESERVED
RANDOM NUMBER
GENERATOR
0x4004 0414
0x4004 0400
RESERVED
PROGRAMMABLE
CRC ENGINE
0x4004 000C
0x4004 0000
RESERVED
SPORT 0
0x4003 8078
0x4003 8000
RESERVED
SPIH 0 MASTER/SLAVE
0x4002 4038
0x4002 4000
RESERVED
GPIO
0x4002 00B4
0x4002 0000
RESERVED
FLASH CONTROLLER
0x4001 8088
0x4001 8000
RESERVED
Figure 22. ADuCM3027/ADuCM3029 Memory Map—SRAM Mode 0
CACHE CONTROLLER
The ADuCM3027/ADuCM3029 MCUs have an optional 4 kB
instruction cache. In certain applications, enabling the cache
and executing the code can result in lower power consumption
rather than operating directly from flash. When enabling the
cache controller, 4 kB of instruction SRAM is reserved as cache
memory. In hibernate mode, the cache memory is not retained.
SYSTEM AND INTEGRATION FEATURES
The ADuCM3027/ADuCM3029 MCUs provide several features
that ease system integration.
Reset
There are four types of resets: external, power-on, watchdog
timeout, and software system reset. The software system reset is
provided as part of the ARM Cortex-M3 core.
The SYS_HWRST pin is toggled to perform a hardware reset.
Booting
The ADuCM3027/ADuCM3029 MCUs support two boot
modes: booting from internal flash and upgrading software
through UART download. If SYS_BMODE0 (Pin P1_01) is
pulled low during power-up or a hard reset, the MCU enters
into serial download mode. In serial download mode, an
on-chip routine initiates in the kernel, which configures the
UART port and communicates with the host to manage the
firmware upgrade via a specific serial download protocol.
Table 22. Boot Modes
Boot Mode
Description
0
UART download mode.
1
Flash boot. Boot from integrated flash memory.
Power Management
The ADuCM3027/ADuCM3029 MCUs have an integrated
power management system that optimizes performance and
extends battery life of the devices.
The power management system consists of the following:
•
Integrated 1.2 V low dropout regulator (LDO) and optional
capacitive buck regulator
•
Integrated power switches for low standby current in
hibernate and shutdown modes.
Additional power management features include the following:
•
Customized clock gating for active and Flexi™ modes
•
Power gating to reduce leakage in hibernate and shutdown
modes
•
Flexible sleep modes
•
Shutdown mode with no retention
•
Optional high efficiency buck converter to reduce power
•
Integrated low power oscillators
Power Modes
The PMU provides control of the ADuCM3027/ADuCM3029
power modes and allows the ARM Cortex-M3 to control the
clocks and power gating to reduce the power consumption.



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