Data Sheet

ADuCM3027/ADuCM3029

Rev. B | Page 5 of 39

POWER SUPPLY CURRENT SPECIFICATIONS

Active Mode

Table 4.

Parameter

Test Conditions/Comments

Buck Enabled

0.40 2.71

mA

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 6.5 MHz

0.98 1.29

mA

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz

1.28 1.64

mA

Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz

0.95 1.36

mA

Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz

1.08 1.43

mA

Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

1.37 1.78

mA

Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

1.08 1.49

mA

Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz

Dynamic Current

30

µA/MHz Code executing from flash, cache enabled

1.75 8.05

mA

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz

2.34 3.0

mA

Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz

1.78 2.48

mA

Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz

1.99 2.67

mA

Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

2.55 3.29

mA

Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

2.03 2.74

mA

Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz

60

µA/MHz Code executing from flash, cache enabled

1

2

3

The code being executed is a prime number generation in a continuous loop, with HFOSC as the system clock source.

Flexi Mode

Table 5.

Parameter

Test Conditions/Comments

FLEXI™ MODE

Buck Enabled

0.3

0.67

mA

Peripheral clocks off

0.39

0.80

mA

Peripheral clocks on, PCLK = 26 MHz

Buck Disabled

0.52

1.11

mA

Peripheral clocks off

0.7

1.38

mA

Peripheral clocks on, PCLK = 26 MHz

1

2