ADUCM3029BCBZ-R7 datasheet(25/39 Pages) AD

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Data Sheet

ADuCM3027/ADuCM3029

Rev. B | Page 25 of 39

Several power modes are available. Each mode provides an

additional low power benefit with a corresponding reduction in

functionality.

Active Mode

In active mode, all peripherals can be enabled. Active power is

managed by optimized clock management. See Table 4 for

details on active mode power.

Flexi Mode

In Flexi mode, the ARM Cortex-M3 core is clock gated, but the

remainder of the system is active. No instructions can be

executed in this mode, but DMA transfers can continue

between peripherals and memory as well as memory to

memory. See Table 5 for details on Flexi mode power.

Hibernate Mode

This mode provides state retention, configurable SRAM and

port pin retention, a limited number of wake-up interrupts

(XINT0_WAKEn and UART0_RX), and, optionally, two

RTCs—RTC0 and RTC1 (FLEX_RTC).

Shutdown Mode

This mode is the deepest sleep mode, in which all the digital

and analog circuits are powered down with an option to wake

from four possible wake-up sources: three external interrupts

and RTC0. The RTC0 can be optionally enabled in this mode

and the device can be periodically woken up by the RTC0

interrupt. See Table 6 for deep sleep (hibernate and shutdown)

mode specifications.

The following features are available for power management and

control:

•

A voltage range of 1.74 V to 3.6 V using a single supply

(such as the CR2032 coin cell battery).

•

GPIOs are driven directly from the battery. The pin state is

retained in hibernate and shutdown modes. The GPIO

configuration is only retained in hibernate mode.

•

Wake-up from external interrupt (via GPIOs), UART0_RX

interrupt, and RTCs for hibernate mode.

•

Wake-up from external interrupt (via GPIOs) and RTC0

for shutdown mode.

•

Optional high power buck converter for 1.2 V full on

support (for MCU use only). See Figure 23 for the

suggested external circuitry.

BUCK

ENABLED

LDO

VDCDC_CAP1P

VBAT

NOTES

1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED,

THE FOLLOWING PINS MUST BE LEFT UNCONNECTED:

VDCDC_CAP1P, VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N

0.1µF

0.47µF

0.1µF

VDCDC_CAP1N

VDCDC_OUT

VDCDC_CAP2P

0.47µF

VLDO_OUT

VDCDC_CAP2N

Figure 23. Buck Enabled Design

For designs in which the optional buck is not used, the

following pins must be left unconnected: VDCDC_CAP1P,

VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, and

VDCDC_CAP2N.

Security Features

The ADuCM3027/ADuCM3029 MCUs provide a combination

of hardware and software protection mechanisms that lock out

access to the devices in secure mode but grant access in open

mode. These mechanisms include password protected slave

boot mode (UART), as well as password protected serial wire

debug (SWD) interfaces.

Mechanisms are provided to protect the device contents (flash,

SRAM, CPU registers, and peripheral registers) from being read

through an external interface by an unauthorized user, which is

referred to as read protection.

It is possible to protect the device from being reprogrammed in

circuit with unauthorized code. This is referred to as in circuit

write protection.

The devices can be configured with no protection, read

protection, or read and in circuit write protection. It is not

necessary to provide in circuit write protection without read

protection.

Cryptographic Accelerator

The cryptographic accelerator is a 32-bit APB DMA capable

peripheral. There are two 32-bit buffers provided for data

input/output operations. These buffers read in or read out

128 bits in four data accesses. Big endian and little endian data

formats are supported, as are the following modes:

•

Electronic code book (ECB) mode—AES mode

•

Counter (CTR) mode

•

Cipher block chaining (CBC) mode

•

Message authentication code (MAC) mode

•

Cipher block chaining-message authentication code

(CCM/CCM*) mode

•

SHA-256 modes

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