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ADUCM3029BCPZ-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADUCM3029BCPZ-R7
功能描述  Ultra Low Power Arm Cortex-M3 MCU with Integrated Power Management
PDF  39 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADUCM3029BCPZ-R7 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
ADuCM3027/ADuCM3029
Rev. B | Page 7 of 39
ADC SPECIFICATIONS
Table 7.
Parameter1, 2
Min
Typ3
Max
Unit
Test Conditions/Comments
INTEGRAL NONLINEARITY ERROR
64-Lead LFCSP
±1.6
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
64-Lead LFCSP
±1.4
LSB
3.0 V (VBAT)/2.5 V (internal/external VREF)4
54-Ball WLCSP
±1.8
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
DIFFERENTIAL NONLINEARITY ERROR
64-Lead LFCSP
−0.7 to +1.15
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
64-Lead LFCSP
−0.7 to +1.1
LSB
3.0 V (VBAT)/2.5 V (internal/external VREF)4
54-Ball WLCSP
−0.75 to +1.2
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
OFFSET ERROR
64-Lead LFCSP
±0.5
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
64-Lead LFCSP
±0.5
LSB
3.0 V (VBAT)/2.5 V (external VREF)4
54-Ball WLCSP
±0.5
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
GAIN ERROR
64-Lead LFCSP
±2.5
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
64-Lead LFCSP
±0.5
LSB
3.0 V (VBAT)/2.5 V (external VREF)4
54-Ball WLCSP
±3.0
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
VBAT_ADC CURRENT (IVBAT_ADC)5
64-Lead LFCSP
104
μA
1.8 V (VBAT)/1.25 V (internal VREF)6
64-Lead LFCSP
131
μA
3.0 V (VBAT)/2.5 V (internal VREF)6
54-Ball WLCSP
108
μA
1.8 V (VBAT)/1.25 V (internal VREF)6
INTERNAL REFERENCE VOLTAGE
1.25
V
Internal reference, 1.25 V selected
2.50
V
Internal reference, 2.5 V selected
INTEGRAL NONLINEARITY ERROR
64-Lead LFCSP
1.22
1.25
1.275
V
1.25 V (internal)7
64-Lead LFCSP
2.45
2.5
2.545
V
2.5 V (internal)
54-Ball WLCSP
1.22
1.25
1.275
V
1.25 V (internal)
54-Ball WLCSP
2.45
2.5
2.545
V
2.5 V (internal)
ADC SAMPLING FREQUENCY (fS)8
0.01
1.8
MSPS
1 The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs.
2 The specifications are characterized after performing internal ADC offset calibration.
3 TJ = 25°C.
4 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode, 400,000 samples end point method used.
5 Current consumption from VBAT_ADC supply when ADC is performing the conversion.
6 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode.
7 No load current, CL = 0.1 μF and 4.7 μF, reference buffer low power mode is enabled.
8 Effects of analog source impedance must be considered when selecting ADC sampling frequency.



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