ADUCM3029BCPZ-R7 datasheet(22/39 Pages) AD

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ADuCM3027/ADuCM3029

Data Sheet

Rev. B | Page 22 of 39

THEORY OF OPERATION

ARM CORTEX-M3 PROCESSOR

The ARM Cortex-M3 core is a 32-bit reduced instruction set

computer (RISC). The length of the data can be 8 bits, 16 bits,

or 32 bits. The length of the instruction word is 16 bits or 32 bits.

The processor has the following features:



Cortex-M3 architecture



Thumb-2 instruction set architecture (ISA)

technology



Three-stage pipeline with branch speculation



Low latency interrupt processing with tail chaining



Single-cycle multiply



Hardware divide instructions



Nested vectored interrupt controller (NVIC)

(64 interrupts and 8 priorities)



Two hardware breakpoints and one watchpoint

(unlimited software breakpoints using Segger JLink)



Memory protection unit (MPU)



Eight region MPU with subregions and background

region



Programmable clock generator unit



Configurable for ultra low power operation



Deep sleep mode, dynamic power management



Programmable clock generator unit

ARM Cortex-M3 Memory Subsystem

The memory map of the ADuCM3027/ADuCM3029 is based

on the Cortex-M3 model from ARM. By retaining the standardized

memory mapping, it is easier to port applications across M3

platforms.

The ADuCM3027/ADuCM3029 application development is

based on memory blocks across code/SRAM regions. Internal

memory is available via internal SRAM and internal flash.

Code Region

Accesses in this region (0x0000 0000 to 0x0001 FC00 for the

ADuCM3027 and 0x0000 0000 to 0x0003 FFFF for the

ADuCM3029) are performed by the core and target the

memory and cache resources.

SRAM Region

Accesses in this region (0x2000 0000 to 0x2004 7FFF) are

performed by the ARM Cortex-M3 core. The SRAM region of

the core can otherwise act as a data region for an application.



Internal SRAM data region. This space can contain read/write

data. Internal SRAM can be partitioned between code and

data (SRAM region in M3 space) in 32 kB blocks. Access to

this region occurs at core clock speed with no wait states.



It also supports read/write access by the ARM Cortex-M3

core and read/write DMA access by system devices. It

supports exclusive memory accesses via the global

exclusive access monitor within the Cortex-M3 platform.



System memory mapped registers (MMRs). Various system

MMRs reside in this region.

System Region

Accesses in this region (0xE000 0000 to 0xF7FF FFFF) are per-

formed by the ARM Cortex-M3 core and are handled within

the Cortex-M3 platform.



CoreSight™ ROM. The read

-only memory (ROM) table

entries point to the debug components of the processor.



ARM APB Peripheral. This space is defined by ARM and

occupies the bottom 256 kB/128 kB of the system (SYS) region

(0xE000 0000 to 0xE004 0000) depending on the device used.

The space supports read/write access by the M3 core to the

internal peripherals of the ARM core (NVIC, system control

space (SCS), wake-up interrupt controller (WIC)), and

CoreSight ROM. It is not accessible by system DMA.

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