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ADUCM3029BCPZ-R7 数据表(PDF) 8 Page - Analog Devices |
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ADUCM3029BCPZ-R7 数据表(HTML) 8 Page - Analog Devices |
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8 / 39 page ![]() ADuCM3027/ADuCM3029 Data Sheet Rev. B | Page 8 of 39 SYSTEM CLOCKS External Crystal Oscillator Specifications Table 8. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOW FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (LFXTAL) Frequency fLFXTAL 32,768 Hz External Capacitance from SYS_LFXTAL_IN Pin to Ground and from SYS_LFXTAL_OUT Pin to Ground CLFXTAL 6 10 pF External capacitors on SYS_LFXTAL_IN and SYS_LFXTAL_OUT pins must be selected considering the printed circuit board (PCB) trace capacitance due to routing Crystal Equivalent Series Resistance ESRLFXTAL 30 kΩ HIGH FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (HFXTAL) Frequency fHFXTAL 26 MHz External Capacitance from SYS_HFXTAL_IN Pin to Ground and from SYS_HFXTAL_OUT Pin to Ground CHFXTAL 20 pF External capacitors on SYS_HFXTAL_IN and SYS_HFXTAL_OUT pins must be selected considering the PCB trace capacitance due to routing Crystal Equivalent Series Resistance ESRHFXTAL 50 Ω On-Chip RC Oscillator Specifications Table 9. Parameter Symbol Min Typ Max Unit LOW FREQUENCY RC OSCILLATOR (LFOSC) Frequency fLFOSC 30,800 32,768 34,407 Hz HIGH FREQUENCY RC OSCILLATOR (HFOSC) Frequency fHFOSC 25.09 26 26.728 MHz System Clocks and PLL Specifications Table 10. Parameter Symbol Min Typ Max Unit PLL SPECIFICATIONS PLL Input Clock Frequency1 fPLLIN 16 26 MHz PLL Output Clock Frequency2, 3 fPLLOUT 16 60 MHz System Peripheral Clock (PCLK) Frequency fPCLK 0.8125 26 MHz Advanced High Performance Bus Clock (HCLK) Frequency fHCLK 0.8125 26 MHz 1 The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC). 2 For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13, PLL_NSEL = 26, PLL_DIV2 = 1 for PLL input clock = 16 MHz. 3 For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8, PLL_NSEL = 30, PLL_DIV2 = 0 for 16 MHz. |
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