Data Sheet

ADuCM3027/ADuCM3029

Rev. B | Page 9 of 39

TIMING SPECIFICATIONS

Reset Timing

Table 11.

Parameter

Symbol

Min

Typ

Max

Unit

RESET TIMING REQUIREMENTS

4

µs

1

Applies after power-up sequence is complete.

SYS_HWRST

Figure 2. Reset Timing

Serial Ports Timing

Table 12.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

EXTERNAL CLOCK SERIAL PORTS

Timing Requirements

5

ns

Externally generated frame sync

in transmit or receive mode

5

ns

Externally generated frame sync

in transmit or receive mode

5

ns

8

ns

38.5

ns

77

ns

Frame Sync Delay After SPT_CLK

20

ns

Internally generated frame sync in

transmit or receive mode

Frame Sync Hold After SPT_CLK

2

ns

Internally generated frame sync in

transmit or receive mode

Transmit Data Delay After Transmit SPT_CLK

20

ns

Transmit Data Hold After Transmit SPT_CLK

1

ns

INTERNAL CLOCK SERIAL PORTS

Receive Data Setup Before SPT_CLK

25

ns

Receive Data Hold After SPT_CLK

0

ns

Switching Characteristics

20

ns

Internally generated frame sync in

transmit or receive mode

−8

ns

Internally generated frame sync in

transmit or receive mode

20

ns

−7

ns

SPT_CLK Width

ns

SPT_CLK Period

ns

Not shown in Figure 3 to Figure 7

ENABLE AND THREE-STATE SERIAL PORTS

Switching Characteristics

5

ns

160

ns

1

This specification is referenced to the sample edge.

2

This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK.

3

These specifications are referenced to the drive edge.