ADP1974

Data Sheet

Rev. 0 | Page 6 of 19

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADP1974

TOP VIEW

(Not to Scale)

DH

VREG

VIN

SYNC

MODE

EN

DL

FAULT

GND

DT

SCFG

SS

COMP

DMAX

FREQ

CL

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DL

Logic Drive Output for the External Low-Side MOSFET Driver.

2

DH

Logic Drive Output for the External High-Side MOSFET Driver.

3

VREG

Internal Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 μF or greater from this pin

to ground is required.

4

VIN

High Input Voltage Supply Pin (6 V to 60 V). Bypass this pin with a 4.7 μF capacitor to ground.

5

EN

Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.

6

MODE

Mode Select. Drive MODE logic low to place the device in boost (recycle) mode. Drive MODE logic high to place

the device in buck (charge) mode of operation. The MODE status is sampled at EN rising or FAULT falling (see the

Operating Modes section).

7

SYNC

Synchronization Pin. This pin is configured as an input (slave mode) with SCFG < 4.51 V to synchronize the ADP1974

to an external clock. This pin is an open-collector driver output with SCFG > 4.53 V (or SCFG connected to VREG).

When configured as an output, SYNC is used to synchronize with other channels; a 10 kΩ resistor to VREG can be

used as a pull-up.

8

FAULT

Fault Input Pin. Drive FAULT low to disable the DL and DH drivers in the event of a fault. Drive FAULT high to enable

the DL and DH drivers. FAULT can also reset the mode of operation as described in the Operating Modes section.

This pin was designed to interface with the overcurrent protection (OCP) or overvoltage protection (OVP) fault

condition on the AD8450/AD8451.

9

COMP

PWM Modulator Input. This pin interfaces with an error amplifier output signal from the AD8450/AD8451. The

signal on this pin is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin

floating; see the External COMP Control section for additional details.

10

SS

Soft Start Control Pin. A capacitor connected from SS to ground sets the soft start ramp time. Soft start controls the

DL and DL duty cycle during power-up to reduce the inrush current. Drive SS below 0.5 V to disable switching of DL

and DH. During soft start, the ADP1974 operates in pseudosynchronous mode (see the Soft Start section).

11

DMAX

Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 97%

internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this pin

is internally pulled up to VREG.

12

FREQ

Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between 50 kHz

and 300 kHz. When the ADP1974 is synchronized to an external clock (slave mode), set the slave frequency to 90%

13

SCFG

input with no phase shift. If SCFG is left floating, the SYNC pin is internally tied to VREG, and SYNC is configured as

an output.

14

DT

Dead Time Programming Pin. Connect an external resistor between this pin and ground to set the dead time.

Do not leave this pin floating.

15

GND

Power and Analog Ground Pin.

16

CL

Current-Limit Programming Pin. Connect a current sense resistor in series with the low-side FET source to measure

the peak current in the inductor. The current-limit thresholds can operate with a 20 kΩ resistor as described in the

Peak Current-Limit Hiccup Implementation section.