ADP1974ARUZ-R7 datasheet(15/19 Pages) AD

15 / 19 page

Data Sheet

ADP1974

Rev. 0 | Page 15 of 19

Selecting RFREQ for a Slave Device

To configure the ADP1974 as a slave device, drive VSCFG < 4.53 V.

When functioning as a slave device, the ADP1974 operates at

the frequency of the external clock applied to the SYNC pin. To

ensure proper synchronization, select RFREQ to set the frequency

to a value slightly slower than that of the master clock by using

the following equation:

RFREQ (SLAVE) = 1.11 × RFREQ (MASTER)

(6)

where:

RFREQ (SLAVE) is the resistor value that appropriately scales the

frequency for the slave device, and 1.11 is the RFREQ slave to

master ratio for synchronization.

RFREQ (MASTER) is the resistor value that corresponds to the

frequency of the master clock applied to the SYNC pin.

The frequency of the slave device is set to a frequency slightly

lower than that of the master device to allow the digital

synchronization loop of the ADP1974 to synchronize to the

master clock period. The slave device can synchronize to a

master clock frequency running between 2% to 20% higher

than the slave clock frequency. Setting RFREQ(SLAVE) to 1.11× larger

than RFREQ(MASTER) runs the synchronization loop in approximately

the center of the adjustment range.

Programming the External Clock Phase Shift

If a phase shift is not required for slave devices, connect the

SCFG pin of each slave device to ground. For devices that

require a phase shifted version of the synchronization clock that

is applied to the SYNC pin of the slave devices, connect a

resistor (RSCFG) from SCFG to ground to program the desired

phase shift. To determine the RSCFG for a desired phase shift

(φSHIFT), start by calculating the frequency of the slave clock

(fSLAVE).

(SLAVE)

FREQ

SLAVE

(kHz) 

(7)

Next, calculate the period of the slave clock.



(kHz)

μs





SLAVE

(8)

where:

tSLAVE is the period of the slave clock in μs.

fSLAVE is the frequency of the slave clock in kHz.

Next, determine the phase time delay (tDELAY) for the desired

phase shift (φSHIFT) using the following equation:



 

360

μs

SLAVE

SHIFT

DELAY







(9)

where:

tDELAY is the phase time delay in μs.

φSHIFT is the desired phase shift.

Lastly, use the following equation to calculate tDELAY:

RSCFG (kΩ) = 0.45 × RFREQ(SLAVE) (kΩ) + 50 × tDELAY (μs)

(10)

where:

RSCFG is the corresponding resistor for the desired phase shift

in kHz. See Figure 19 for the RSCFG vs. tDELAY graph.

When using the phase shift feature, connect a capacitor of 47 pF

or greater in parallel with RSCFG.

Alternatively, the SCFG pin can be controlled with a voltage source.

When using an independent voltage source, ensure VSCFG ≤ VREG

under all conditions. When the ADP1974 is disabled via the

EN pin or UVLO, VREG = 0 V, and the voltage source must be

adjusted accordingly to ensure VSCFG ≤ VREG.

Figure 29 shows the internal voltage ramp of the ADP1974. The

voltage ramp is a well controlled 4 V p-p.

4.5V

0.5V

0.01T

0.99T

Figure 29. Internal Voltage Ramp

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