Data Sheet

ADP1974

Rev. 0 | Page 13 of 19

NEGATIVE CURRENT-LIMIT DETECTION (BUCK

MODE)

The ADP1974 detects negative current in the inductor in buck

mode with a comparator on the CL pin set to 450 mV, as shown in

Figure 27. When the current in the low-side FET drops below the

which is used as a negative current limit in buck mode, detecting the

equivalent of ½ the positive peak current.

VREG

CL

450mV

20µA

20kΩ

M2

MODE

SELECT

H

H = BUCK

L = BOOST

L

Figure 27. Block Diagram for Negative Current-Limit Protection

PWM FREQUENCY CONTROL

The FREQ, SYNC, and SCFG pins determine the source,

frequency, and synchronization of the clock signal that operates

the PWM control of the ADP1974.

Internal Frequency Control

The ADP1974 frequency can be programmed with an external

resistor connected between FREQ and ground. The frequency

range can be set from a minimum of 50 kHz to a maximum of

(typical), or if the SCFG pin is left floating, the SYNC pin is

configured as an output, and the ADP1974 operates at the

the open-drain device. The output clock of the SYNC pin operates

with a 50% (typical) duty cycle. In this configuration, the SYNC pin

can synchronize other switching regulators in the system to the

ADP1974. When the SYNC pin is configured as an output, an

external pull-up resistor is needed from the SYNC pin to an

external supply. The VREG pin of the ADP1974 can be used as

the external supply rail for the pull-up resistor.

External Frequency Control

input, the ADP1974 synchronizes to the external clock applied

to the SYNC pin, and the ADP1974 operates as a slave device.

This synchronization allows the ADP1974 to operate at the

same switching frequency with the same phase as other

switching regulators or devices in the system. When operating

frequency that approximates but is not equal to the external

clock frequency, which is further explained in the Applications

Information section.

Operating Frequency Phase Shift

4.25 V, the SYNC pin is configured as an input, and the ADP1974

synchronizes to a phase shifted version of the external clock

applied to the SYNC pin. To adjust the phase shift, place a resistor

supply ripple for systems containing multiple switching power

supplies.

MAXIMUM DUTY CYCLE

The maximum duty cycle of the ADP1974 can be externally

programmed to any value between 0% and 97% via an external

resistor on the DMAX pin connected from DMAX to ground.

The maximum duty cycle defaults to 97% if DMAX is left floating,

if DMAX is tied to VREG, or if DMAX is programmed to a

value greater than 97%.

EXTERNAL FAULT SIGNALING

The ADP1974 is equipped with a FAULT pin that signals the

ADP1974 when an external fault condition occurs. The external

fault signal stops PWM operation of the system to avoid damage

to the application and components. When a voltage less than

1.05 V (typical) is applied to the FAULT pin, the ADP1974 is

disabled. In this state, the DL and DH PWM drive signals are

both driven low to prevent switching, and the soft start capacitor

than 1.2 V (typical) is applied to the FAULT pin, the ADP1974

begins switching. A voltage ranging from 0 V to 60 V can be

applied to the FAULT pin of the ADP1974.

THERMAL SHUTDOWN (TSD)

The ADP1974 has a TSD protection circuit. The thermal shutdown

triggers and disables switching when the junction temperature

of the ADP1974 reaches 150°C (typical). While in TSD, the DL

ground, and VREG remains high. When the junction temperature

decreases to 135°C (typical), the ADP1974 restarts the application

control loop.