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ADP1974ARUZ-R7 数据表(PDF) 16 Page - Analog Devices |
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ADP1974ARUZ-R7 数据表(HTML) 16 Page - Analog Devices |
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16 / 19 page ![]() ADP1974 Data Sheet Rev. 0 | Page 16 of 19 Programming the Dead Time To adjust the dead time on the synchronous DH and DL outputs, connect a resistor (RDT) from DT to GND and bypass with a 47 pF capacitor. Select RDT for a given dead time using Figure 30 or calculate RDT using the following equations. To reach a single equation for RDT, combine the equations for VDT and RDT. 3.76 28.51 ns V DEAD DT DT t I V (11) DT DT DT I V R (12) where: VDT is the DT pin programming voltage. IDT is the 20 μA (typical) internal current source. tDEAD is the desired dead time in ns. RDT is the resistor value in kΩ for the desired dead time. To calculate RDT for a given tDEAD, the resulting equation used is 3.76 28.51 ns kΩ DEAD DT t R (13) 0 25 50 75 100 125 150 175 0 100 200 300 400 500 600 700 tDEAD (ns) Figure 30. DT Pin Resistance (RDT) vs. Dead Time (tDEAD) PROGRAMMING THE MAXIMUM DUTY CYCLE The ADP1974 is designed with a 97% (typical) maximum internal duty cycle. By connecting a resistor from DMAX to ground, the maximum duty cycle can be programmed at any value from 0% to 97%, by using the following equation: 5 . 10 5 . 21 % FREQ DMAX FREQ MAX R R V D (14) where: DMAX is the programmed maximum duty cycle. VFREQ = 1.252 V (typical). RDMAX is the value of the resistance used to program the maximum duty cycle. RFREQ is the frequency set resistor used in the application. The DMAX current source is equivalent to the programmed current of the FREQ pin: FREQ FREQ FREQ DMAX R V I I (15) where IDMAX = IFREQ is the current programmed on the FREQ pin. DUTY CYCLE (%) 0 50 100 150 200 250 300 350 400 450 020 60 80 100 40 TA = +25°C Figure 31. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VCOMP = 5 V The maximum duty cycle of the ADP1974 is 97% (typical). If the resistor on DMAX sets a maximum duty cycle larger than 97%, the ADP1974 defaults to its internal maximum. If the 97% internal maximum duty cycle is sufficient for the application, tie the DMAX pin to VREG or leave it floating. The CDMAX capacitor connected from the DMAX pin to the ground plane must be 47 pF or greater. ADJUSTING THE SOFT START PERIOD The ADP1974 has a programmable soft start feature that prevents output voltage overshoot during startup. Refer to Figure 22 for a soft start diagram. To calculate the delay time before switching is enabled (tREG), use the following equation: SS SS REG C I t 0.52 (16) where: ISS = 5 μA, typical. CSS is the soft start capacitor value. The output voltage rising ramp is then proportional to the ramp on SS and the input voltage of the ADP1974. SS SS RAMP C I t 4 (V/s) ) s ( RAMP IN OUT t V Time V RAMP_RATE |
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