ADP1974

Data Sheet

Rev. 0 | Page 12 of 19

0.5V

4.5V

2.5V

BOOST MODE CONFIGURATION

MODE ≤ 1.05V (TYPICAL)

COMP

0V

DH

DL

0V

INTERNAL RAMP

(4V p-p)

VREG (5V TYPICAL)

VREG (5V TYPICAL)

0V

Figure 23. Drive Signal Diagram for Boost Configuration

BUCK MODE CONFIGURATION

MODE ≥ 1.20V (TYPICAL)

0.5V

4.5V

COMP

0V

DH

DL

0V

INTERNAL RAMP

(4V p-p)

VREG (5V TYPICAL)

VREG (5V TYPICAL)

0V

2.5V

Figure 24. Drive Signal Diagram for Buck Configuration

PWM DRIVE SIGNALS

The ADP1974 has two 5 V logic level output drive signals, DH

and DL that are compatible with drivers similar to the ADuM7223.

The DH and DL drive signals synchronously turn on and off the

high-side and low-side switches driven from the external driver.

The ADP1974 provides resistor programmable dead time to

prevent the DH and DL pins from transitioning at the same

time, as shown in Figure 25. Connect a resistor to ground on

the DT pin to program the dead time.

DL

DH

When driving capacitive loads with the DH and DL pins, a 20 Ω

resistor must be placed in series with the capacitive load to reduce

ground noise and ensure signal integrity.

EXTERNAL COMP CONTROL

The ADP1974 COMP pin is the input to the PWM modulator

comparator. The ADP1974 uses a voltage mode control that

compares an error signal, applied to the COMP pin by an

external error amplifier, such as the AD8450/AD8451, to an

internal 4 V p-p triangle waveform. As the load changes, the

error signal increases or decreases. The internal PWM comparator

determines the appropriate duty cycle drive signal by monitoring

the error signal at the COMP pin and the internal 4 V p-p ramp

signal. The internal PWM comparator subsequently drives the

external gate driver at the determined duty cycle through the DH

and DL signals.

The functional voltage range of the COMP pin is from 0 V to

4.5 V, the ADP1974 operates the DH and DL outputs at the

maximum programmed duty cycle (or 97% whichever is the

DH or DL output at a 0% duty cycle, according to the operating

mode, while the complementary DL or DH output is driven at a

100% duty cycle. The input to the COMP pin must never

exceed the 5.5 V absolute maximum rating.

The DL and DH signals swing from VREG (5 V typical) to

ground. The external FET driver used must have input control

pins compatible with a 5 V logic signal.

PEAK CURRENT-LIMIT HICCUP IMPLEMENTATION

The ADP1974 features a peak hiccup current-limit implementation

measured on the low-side FET across a sense resistor. When the

peak inductor current exceeds the programmed current limit

for more than 500 consecutive clock cycles, 5.2 ms (typical) for

a 100 kHz programmed frequency, the peak hiccup current-

limit condition occurs. If the overcurrent exist for less than

500 consecutive cycles, the counter is reset to zero. When the

overcurrent condition occurs, the SS pin is discharged through

a 1 kΩ resistor, and the drive signals, DL and DH, are disabled

for the next 500 clock cycles to allow the FETs to cool down (hiccup

mode). When the 500 clock cycles expire, the ADP1974 restarts

through a new soft start cycle.

Figure 26 shows the current-limit block diagram for peak current-

limit protection.

VREG

CL

500mV

300mV

20µA

20kΩ

M2

MODE

SELECT

H

H = BUCK

L = BOOST

H

L

L

Figure 26. Current-Limit Block Diagram for Peak Current-Limit Protection

The current-limit threshold is set internally based on the mode

with 400 mV across it due to the 20 μA current source. More

information on how to set the current limit is available in the

Applications Information section.