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ADP8140ACPZ-1-R7 数据表(PDF) 12 Page - Analog Devices |
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ADP8140ACPZ-1-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 23 page ![]() ADP8140 Data Sheet Rev. B | Page 12 of 23 Figure 21. Start-Up Timing and Signals CURRENT SINKS The ADP8140 contains four internal current sinks. Each current sink is capable of delivering 125 μA to 500 mA. To ensure accurate regulation, the voltage on the current sinks must be greater than the maximum headroom voltage given in Table 1. For additional information on the headroom voltage, see Figure 7 to Figure 9. All current sinks have their maximum current set by the external resistor, RSET. To determine the value of RSET, use Equation 1. A graph of sink current vs. RSET is shown in Figure 14. (mA) 2560 ) (kΩ SINK SET I R (1) Multiple sinks can be combined together for higher currents per LED string. For example, two sinks can be shorted together to drive two strings of LEDs, each at up to 1 A, or four sinks combined to drive one string of LEDs at up to 2.0 A. A resistor must always be connected to the ISET pin. However, in the event that ISET is accidentally left open, the ADP8140 defaults to a typical current of 15 mA (typical) per sink. If ISET is accidentally shorted to GND, the ADP8140 limits the current per sink to 570 mA (typical) and shuts down the power stage ( A FAULTE A goes low and FB_OUT and COMP are disabled). Each current sink has a maximum rated voltage of 20 V. However, the maximum output voltage driving all the current sinks, through the LEDs, is allowed to exceed 20 V. The LEDs drop enough voltage so that the SINKx voltage remains close to the FB_OUT EA accuracy value, VEA(REF) (where REF is the reference voltage). Because the ADP8140 controls the power stage, the voltage is not present when off or during a fault. Therefore, the ADP8140 can be safely used in conjunction with power supplies that produce over 100 V for their output. POWER CONTROL OPERATION The ADP8140 controls a power stage with its COMP and FB_OUT pins. The power stage allows the IC to optimize the efficiency and protection of the LEDs. The ADP8140 operates in two power control modes: error amplifier and low gain buffer. The MODE pin is used to select the power control mode. 3.0V VUVLO UVLO VIN REG EN SHUTDOWN SHUTDOWN 100µs VREG OK AND UVLO OK AND EN HIGH DETERMINE MODE STATE ~8ms SINK_EN (INTERNAL) MODE_STATE (INTERNAL) FAULT (EXT RESISTOR PULL-UP) COMP (EA CONFIG) COMP (BUFFER CONFIG) FB_OUT (EA CONFIG) DETERMINE (ONE OF 4 STATES) UNTIL REG OR VIN POWERS DOWN |
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