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ADP8140ACPZ-1-R7 数据表(PDF) 18 Page - Analog Devices |
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ADP8140ACPZ-1-R7 数据表(HTML) 18 Page - Analog Devices |
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18 / 23 page ![]() ADP8140 Data Sheet Rev. B | Page 18 of 23 OPERATING THE ADP8140 FROM HIGHER INPUT VOLTAGES The ADP8140 is capable of operating from an input voltage (VIN) range of 3.0 V to 30 V. However, higher voltages can be used to power the ADP8140 when an appropriate current limiting circuit is used. It is sometimes sufficient to limit the voltage on the VIN pin by placing a Zener diode on VIN and limiting the current with a resistor from the input voltage to the VIN pin. This method can be used if standby power dissipation is not an issue. Alternatively, if the supply voltage range is small, an additional Zener diode between the supply and the VIN pin shifts the voltage at the VIN pin below 30 V. This method adds minimal power dissipation in both standby and active modes. However, a more robust voltage limiter uses a Zener diode, an NPN transistor, and two resistors. This simple circuit, shown in Figure 29, gives the required operating IQ during normal operation but also reduces the standby current when the ADP8140 is disabled. Figure 29. VIN Current Limiting Circuit for High Input Voltages Select VZ to give a voltage well below the 30 V absolute maximum of the VIN pin. With this circuit, the VIN pin voltage is regulated to about VZ − 0.7 V. Select the resistor, RZ, to limit the current when the ADP8140 is disabled yet still provide enough current to reverse bias the Zener diode and drive the NPN transistor when the ADP8140 is active. The current through RZ is given by Z Z CC RZ R V V I A value of 100 μA at the minimum expected VCC is generally sufficient. Even at maximum VCC, this value only contributes a few milliwatts of power dissipation during standby. RLIM limits the maximum current during transients. A value of a few hundred ohms is sufficient. When the ADP8140 is active, the additional worst case power dissipation from this limit circuitry is given by ΔPDISS(ACTIVE) = (VCC(MAX) – VZ(MIN) + 0.7 V) × IQ = (48 V − 24 V + 0.7 V) × 3 mA = 74 mW EFFECT OF LED VF MISMATCH The ADP8140 always controls the FB_OUT pin to regulate the output voltage to provide the minimum amount of headroom voltage required for the current sinks. One of the current sinks is regulated to VEA(REF). Typically, VEA(REF) is either 350 mV or 450 mV (see VEA(350) and VEA(450) in Table 1). The voltage seen on the other three SINKx pins varies based on the distribution of the LED forward voltage, VF. For a given lot of LEDs, the VF and the change in VF with temperature is relatively consistent. Given a VF distribution, the maximum voltage that appears on any of the SINKx pins can be statistically calculated. For example, consider a mean VF of 3.5 V and a normal distribution with a standard deviation of 70 mV. A statistical analysis of such a distribution reveals the maximum voltage that may appear on any of the SINKx pins, as shown in Figure 30). Note that in Figure 30, the maximum value is defined as the average plus six standard deviations (σ) of the distribution. Figure 30. Voltage on SINKx Pins Given a Normal Distribution of VF, Standard Deviation = 70 mV The SINKx voltage found on each pin determines the power that the ADP8140 package must dissipate. Specifically, the ADP8140 power dissipation can be represented as follows: PDISS = (VSINK1 + VSINK2 + VSINK3 + VSINK4) × ILED (2) A statistical analysis based on the VF distribution of the LED can be performed to predict the total power dissipation within the ADP8140. For the same distribution used in Equation 2 and an LED current of 350 mA, Figure 31 gives the average and maximum power dissipations. Note that in Figure 31, the maximum value is defined as the average plus six standard deviations of the distribution. CIN VZ IB RZ RLIM VCC VIN ADP8140 NUMBER OF LEDs PER STRING AVERAGE MAX 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 10 15202530 |
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