Data Sheet

ADP8140

Rev. B | Page 19 of 23

Figure 31. Total Power Dissipation (All Four Strings) for a Normal

MANAGING THE POWER DISSIPATION OF THE

ADP8140

With the predicted power dissipation known, the next step is to

determine if the ADP8140 package is able to dissipate that

power adequately. Use the following to calculate the maximum

power that the ADP8140 is able to dissipate:

= (135 − 105)/12.4 = 2.4 W

where:

(before entering thermal foldback).

Assume that 100% of the power dissipates through the exposed

pad to the board.

The ability of the ADP8140 package to dissipate heat varies if

conditions given in Table 3. Additionally, it is imperative to

follow the layout guidelines given in the Layout Guidelines

section.

LAYOUT GUIDELINES

For optimum performance, follow these layout guidelines:



The exposed pad of the ADP8140 must be properly

connected to a heat sink. Solder the exposed pad to the

PCB and connect it to a large plane of ground metal with

an array of thermal vias.



The ADP8140 is designed for easy layout with single sided

metal core substrates. If FR4 substrate is used, thermal vias

must be used between the LFCSP exposed pad and a large

ground trace on the opposite side of the board.



Place the REG capacitor close to the IC. The location of the

VIN capacitor is not as important.



Place the COMP capacitor(s) and resistor as close to the IC

as possible.



Place the VO_SNS resistors (if used) close to the IC.



If applying an analog dimming voltage to the DIM or VT

pins, placing a bypass capacitor near these pins reduces the

noise on these dimming signals.

ORDERING OPTIONS

The ADP8140 is available in two options. The difference

sinks that control the COMP and FB_OUT voltage.

See Figure 33 to Figure 36 for examples of the ADP8140 used in

various configurations: with a PMOS regulation stage, as a

secondary side controller, with a boost or buck power stage, or

with one power stage.

ADP8140ACPZ-1-R7

using the device with the PMOS power stage or as a secondary

side controller, each current sink can supply up to 350 mA of

LED current at 350 mV of headroom voltage. However, if using

the device to control an SMPS IC, each current sink can supply

up to 500 mA of LED current.

The minimum voltage for all four of the current sinks is used to

control the power regulation (COMP and FB_OUT).

ADP8140ACPZ-2-R7

four of the sinks can be driven to 500 mA in any configuration.

Only the minimum voltage from SINK1, SINK2, and SINK3 is

used to control the FB_OUT and COMP pins. Therefore, this is

the preferred device model if only three LED strings are used in

a system. SINK4 can be left floating or connected to GND. Note

that SINK4 is still enabled; if it is connected to an LED string, it

regulates its current to be the same as the other sinks. Therefore,

SINK4 can be combined with another SINKx pin (for example

to drive two strings at 1 A each).

NUMBER OF LEDs PER STRING

AVERAGE

MAX

0

0

0.5

1.0

1.5

2.0

2.5

3.0

5

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