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ADP8140ACPZ-1-R7 数据表(PDF) 13 Page - Analog Devices |
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ADP8140ACPZ-1-R7 数据表(HTML) 13 Page - Analog Devices |
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13 / 23 page ![]() Data Sheet ADP8140 Rev. B | Page 13 of 23 MODE PIN OPERATION The MODE pin is used to program one of four possible modes of operation. The condition of the MODE pin affects the DIM pin input (see the Reducing the LED Current with the DIM Pin section) and the power control mode (see Power Control Modes section). The MODE pin state is read at power-up only, when VIN crosses the UVLO threshold. After this point, the MODE pin voltage is 0 V. The MODE status cannot change after power-up. Table 5. Modes of Operation Programmed by the MODE Pin MODE Connection DIM Pin Mode Power Control GND Analog voltage Error amplifier 30.1 kΩ to GND Analog voltage Low gain buffer 52.3 kΩ to GND PWM signal Low gain buffer REG PWM signal Error amplifier POWER CONTROL MODES Error Amplifier Power Control In the error amplifier power control mode, the ADP8140 applies the minimum voltage of the four current sinks to the inverting input of an internal error amplifier. The output of this error amplifier connects to the FB_OUT inverting buffer. The FB_OUT pin outputs a current, which indicates power control. A higher FB_OUT sink current indicates that more power is required to the LEDs. A lower FB_OUT sink current indicates that less power is required for the LEDs. This operation makes the FB_OUT ideal for any power control application that does not normally have an error amplifier. The two primary applications for this are as follows: Controlling an optocoupler on the secondary side of an isolated power supply Controlling a PMOS transistor to regulate power in a fixed output voltage supply. Depending on the power stage used, an RC network must be connected to the COMP pin. The COMP pin connects to the output of the FB_OUT transconductance amplifier. To select the COMP resistor and capacitor values, a free simulation tool, ADIsimPE, is available at: www.analog.com/ADIsimPE. Using this tool, and the included ADP8140 circuit model, the loop control and stability can be easily simulated and adjusted for different setups. Figure 22. Error Amplifier Power Control SINK1 SINK2 SINK3 SINK4 ID1 ID2 ID4 ID3 SHUTDOWN SINK CONTROL SINK_EN 8V/15V FB_OUT MIN CH_OVP 5.7V MAX VEA(REF) COMP MIN AND MAX |
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