Preliminary Technical Data

AD7658/AD7657/AD7656

Rev. PrI | Page 11 of 25

PIN FUNCTIONAL DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AD7656

TOP VIEW

(Not to Scale)

PIN 1

IDENTIFIER

DB7/HBEN/DCEN

DB6/SCLK

DB5/DCIN A

DB4/DCIN B

DB3/DCIN C

DB2/SEL C

DB1/SEL B

VDRIVE

DB13

DB12

DB11

DB10/SDATA C

DB9/SDATA B

DB8/SDATA A

DGND

V3

AGND

AGND

V2

AVCC

AVCC

V1

AVCC

AVCC

AVCC

V5

AGND

AGND

V4

AVCC

V6

Table 6. AD7658/AD7657/AD7656 Pin Function Descriptions

Pin Mnemonic

Description

REFCAPA, REFCAPB,

REFCAPC

Decoupling capacitors are connected to these pins to decouple the reference buffer for each

ADC pair. Each REFCAP pin should be decoupled to AGND using 10 µF and 100 nF capacitors.

V1 – V6

Analog Input1-6. These are six single-ended Analog inputs. The Analog input range on these

channels is ddetermined by the RANGE pin.

AGND

Analog Ground. Ground reference point for all analog circuitry on the

AD7658/AD7657/AD7656. All analog input signals and any external reference signal should be

referred to this AGND voltage. All eleven of these AGND pins should be connected to the

AGND plane of a system. The AGND and DGND voltages ideally should be at the same

potential and must not be more than 0.3 V apart, even on a transient basis.

DVCC

Digital Power. Normally at 5V. The DVCC and AVCC voltages should ideally be at the same

potential and must not be more than 0.3 V apart even on a transient basis. This supply should

be decoupled to DGND. 10 µF and 100 nF decoupling capacitors should be placed on the

DVCC pin.

VDRIVE

Logic power supply input. The voltage supplied at this pin determines at what voltage the

interface will operate. Nominally at the same supply as the supply of the host interface. This

pin should be decoupled to DGND. 10 µF and 100 nF decoupling capacitors should be placed

on the VDRIVE pin.