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Preliminary Technical Data

AD7658/AD7657/AD7656

Rev. PrI | Page 19 of 25

conversion is ± 2 x VREF. When the RANGE pin is a logic low

at the falling edge of the BUSY signal the range for the next

conversion is ± 4 x VREF.

Changing the Analog Input Range(H/S SEL=1)

When the H/S SEL pin is high the range can be changed by

writing to the Control Register. DB12:10 in the Control Register

are used to select the Analog input Ranges for the next

conversion. Each Analog input pair has an associated range bit,

allowing independent ranges to be programmed on each ADC

pair. When the RNGX bit is 1 the Range for the next conversion

is ±2 x VREF. When the RNGX bit is 0 the range for the next

conversion is ±4 x VREF.

SERIAL INTERFACE (SER/PAR = 1)

By pulsing one, two or all three CONVSTX signals the

AD7658/AD7657/AD7656 will simultaneously convert the

selected channel pairs on the rising edge of CONVSTX. The

simultaneous conversions on the selected ADCs are performed

using the on-chip trimmed oscillator. After the rising edge of

CONVSTX the BUSY signal goes high to indicate the

conversion has started. It returns low when the conversion is

complete 3 µs later. The output register will be loaded with the

new conversion results and data can be read from the

AD7658/AD7657/AD7656. To read the data back from the

AD7658/AD7657/AD7656 over the serial interface SER/PAR

should be tied high. The CS and SCLK signal are used to

transfer data from the AD7658/AD7657/AD7656. The

AD7658/AD7657/AD7656 has three DOUT pins, DOUTA,

DOUTB, DOUTC. Data can be read back from the

AD7658/AD7657/AD7656 using one, two or all three DOUT

lines. Figure 9 shows six simultaneous conversions and the read

sequence using three DOUT lines. In figure 8, 32 SCLK

transfers are used to access data from the

AD7658/AD7657/AD7656, two 16 SCLK transfers individually

framed with the CS signal can also be used to access the data on

the three DOUT lines. When operating the

AD7658/AD7657/AD7656 in serial mode with conversion data

being clocked out on all three DOUT line DB0-DB2 should be

tied to VDRIVE. These pins are used to enable the DOUTA –

DOUTC lines respectively.

If it is required to clock conversion data out on two data out

lines then DOUTA and DOUTB should be used. Again to

enable DOUTA and DOUTB, DB0 and DB1 should be tied to

VDRIVE and DB2 should be tied low. When six simultaneous

conversions are performed and only two DOUT lines are used,

a 48 SCLK transfer can be used to access the data from the

AD7658/AD7657/AD7656. The read sequence is shown in

Figure 10 for a simultaneous conversion on all six ADCs using

two DOUT lines. If a simultaneous conversion occurred on all

six ADCs and only two DOUT lines are used to read the results

from the AD7658/AD7657/AD7656, DOUTA will clock out the

result from V1, V2 and V5, while DOUTB will clock out the

results from V3,V4 and V6.

Data can also be clocked out using just one DOUT line, in this

case DOUTA should be used to access the conversion data. To

configure the AD7658/AD7657/AD7656 to operate in this

mode then DB0 should be tied to VDRIVE, DB1 and DB2 should

be tied low. The penalty for using just one DOUT line is the

throughput rate will be reduced. Data can be accessed from the

AD7658/AD7657/AD7656 using one 96 SCLK transfer, three 32

SCLK individually framed transfers or six 16 SCLK individually

framed transfers. In Serial mode the RD signal should be tied

low.

CONVST A,B,C

BUSY

DOUTA

tCONV

DOUTB

DOUTC

tQUIET

SCLK

tACQ

Figure 9. Serial Interface with three DOUT lines.

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