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AD7656 数据表(PDF) 21 Page - Analog Devices |
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AD7656 数据表(HTML) 21 Page - Analog Devices |
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21 / 25 page ![]() Preliminary Technical Data AD7658/AD7657/AD7656 Rev. PrI | Page 21 of 25 devices in Daisy Chain Mode. The CS falling edge is used to frame the serial transfer from the AD7658/AD7657/AD7656 devices, take the bus out of three- state and clock out the MSB of the first conversion result. In the example shown all twelve ADC channels were simultaneously sampled. Two DOUT line are used to read the conversion results in this example. CS frames a 96 SCLK transfer. During the first 48 SCLK the conversion data is transferred from Device #2 to Device #1. DOUT A on device #2 transfers conversion data from V1, V2 and V5 into DCINA in device #1. DOUT B on device #2 transfers conversion results from V3, V4 and V6 to DCIN B in device #1. During the first 48 SCLK device #1 transfers data into the digital host, DOUTA on device #1 transfers conversion data from V1, V2 and V5. DOUTB on device #1 transfers conversion data from V3, V4 and V6. During the last 48 SCLKs device #2 will clock out zeros, device #1 will shift the data it clocked in from device #2 during the first 48 SCLKs into the digital host. This example could also have been implemented using 3 x 32 SCLK individually framed SCLK transfers or 6 x 16 SCLK individually framed SCLK transfers provided DCEN remained high during the transfers. Figure 14 shows the timing if two AD7656 were configured in Daisy chain mode but operating with three DOUT lines. Again assuming a simultaneous sampling of all 12 inputs occurred. During the read operation the CS frames a 64 SCLK transfer. During the first 32 SCLKs of this transfer the conversion results from Device #1 are clocked into the digital host and the conversion results from device #2 are clocked into device #1. During the last 32 SCLKs of the transfer the conversion results from device #2 are clocked out of device #1 and into the digital host. Device #2 will clock out zeros. Digital Host CONVERT CS SCLK AD7656 AD7656 CONVST CONVST CS CS SCLK SCLK DATA IN1 DATA IN2 DOUTA DOUTB DOUTA DOUTB DCINA DCINB DCEN =0 DCEN=1 DEVICE #1 DEVICE #2 Figure 12. Daisy-Chain Configuration DEVICE#1DOUTA MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5 MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 1 2 3 tCONV t1 CONVST A/B/C BUSY SCLK CS 15 16 17 31 32 33 47 48 49 63 65 64 94 95 96 DEVICE#1DOUTB MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6 DEVICE#2DOUTA MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 DEVICE#2DOUTB t17 t18 t19 Figure 13. Daisy-Chain Serial Interface Timing with 2 DOUT lines |
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