AD7658/AD7657/AD7656

Preliminary Technical Data

Rev. PrI | Page 12 of 25

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the

AD7658/AD7657/AD7656. Both DGND pins should connect to the DGND plane of a system.

The DGND and AGND voltages ideally should be at the same potential and must not be more

than 0.3 V apart even on a transient basis.

AVCC

Analog Supply Voltage, 4.5 V to 5.5 V. This is the only supply voltage for ADC cores. The AVCC

and DVCC voltages ideally should be at the same potential and must not be more than 0.3 V

apart even on a transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF

decoupling capacitors should be placed on the AVCC pins.

CONVSTA, B, C

Conversion Start Input A,B,C. Logic Inputs. These inputs are used to initiate conversions on the

ADC pairs. CONVSTA is used to initiate simultaneous conversions on V1 and V2. CONVSTB is

used to initiate simultameous conversions on V3 and V4. CONVSTC is used to initiate

simultaneous conversions on V5 and V6. When CONVSTX switches from low to high the track-

and-hold switch on the selected ADC pairs switches from track to hold and the conversion is

initiated.

CS

Chip Select. Active low logic input. This input frames the data transfer. When both CS and RD

are logic low in parallel mode the output bus is enabled and the conversion result is output on

the Parallel Data Bus lines. When both CS and WR are logic low in parallel mode DB[15:8] are

used to write data to the on-chip control register. In serial mode the CS is used to frame the

serial read transfer.

RD

Read Data. When both CS and RD are logic low in parallel mode the output bus is enabled. In

serial Mode the RD line should be held low.

WR/ REF EN/DISABLE

Write Data/ reference Enable/Disable. When H/S SEL pin is high both CS and WR are logic low

DB[15:8] are used to write data to the internal Control Register. When H/S SEL pin is low this

pin is used to enable or disable the internal Reference. When H/S SEL =0 and REF EN/DISABLE =

0 the internal reference is disabled and an external reference should be applied to this pin.

When H/S SEL = 0 and REF EN/DISABLE = 1 the internal reference is enabled.

BUSY

BUSY Output. Transitions high when a conversion is started and remains high until the

conversion is complete and the conversion data is latched into the Output Data registers.

REFIN/REFOUT

Reference Input/Output. The on-chip reference is available on this pin for use external to the

AD7658/AD7657/AD7656. Alternatively, the internal reference can be disabled and an external

reference applied to this input. See Reference Section.

SER/PAR

Serial/parallel selection Input. When low, the parallel port is selected. When high the serial

interface mode is selected. In serial mode DB[10:8] take on their SDATA [C:A] function, DB[0:2]

take on their DOUT select function, DB[7] takes on its DCEN function. In serial mode DB15 and

DB[13:11] should be tied to DGND.

DB[0]/SEL A

Data Bit [0]/Select DOUT A. When SER/PAR = 0, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1, this pin takes on its SEL A function, it is used to configure the

serial interface. If this pin is 1, the serial interface will operate with one/two/three DOUT ouput

pins and enables DOUT A as a serial output. When operating in serial mode this pin should

always be = 1.

DB[1]/SEL B

Data Bit [1]/Select DOUT B. When SER/PAR = 0, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1, this pin takes on its SEL B function, it is used to configure the

serial interface. If this pin is 1, the serial interface will operate with two/three DOUT ouput pins

and enables DOUT B as a serial output. If this pin is 0 the DOUT B is not enabled to operate as a

serial Data Output pin and only one DOUT output pin is used.

DB[2]/SEL C

Data Bit [2]/Select DOUT C. When SER/PAR = 0, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1, this pin takes on its SEL C function, it is used to configure the

serial interface. If this pin is 1, the serial interface will operate with three DOUT ouput pins and

enables DOUT C as a serial output. If this pin is 0 the DOUT C is not enabled to operate as a

serial Data Output pin.

DB[3]/DCIN C

Data Bit [3]/Daisy Chain in C. When SER/PAR =0, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input C.

DB[4]/DCIN B

Data Bit [4]/Daisy Chain in B. When SER/PAR =0, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input B.

DB[5]/DCIN A

Data Bit [5]/Daisy Chain in A. When SER/PAR is low, this pin acts as a three-state Parallel Digital

Output pin. When SER/PAR is =1 and DCEN = 1, this pin acts as Daisy Chain Input A.

DB[6]/SCLK

Data Bit [6[/Serial Clock. When SER/PAR =0, this pin acts as three-state Parallel Digital Output