AD7658/AD7657/AD7656

Preliminary Technical Data

Rev. PrI | Page 18 of 25

Figure 6. AD7658/AD7657/AD7656 Parallel Interface Timing Diagram (W/B= 0)

LOW BYTE

HIGH BYTE

DB15-DB8

+5

4,

t3

t4

t5

t6

t7

t9

Figure 7. Parallel Interface – Read cycle for Byte mode of operation. (W/B= 1, HBEN = 0)

Software Selection of ADCs

The H/S SEL pin determines the source of the combination of

ADCs that are to be simultaneously sampled. When the H/S

SEL pin is a logic low the combination of channels to be

simultaneously sampled is determined by the CONVSTA,

CONVSTB, and CONVSTC pins. When the H/S SEL pin is a

logic high the combination of channels selected for

simultaneous sampling is determined by the contents of the

Control register DB15 to DB8. In this mode a write to the

Control register is necessary.

The Control register is an 8-bit write only register. Data is

written to this register using the CS and WR pins and DB[15:8]

data pins, see Figure 8. The Control register is shown in Table 8.

To select an ADC pair to be simultaneously sampled, set the

corresponding data line high during the write operation.

The AD7658/AD7657/AD7656 control register allows

individual ranges to be programmed on each ADC pair. DB12

to DB10 in the Control register are used to program the range

on each ADC pair. The AD7658/AD7657/AD7656 allows the

user to select either ± 4 x VREF or ± 2 x VREF as the analog

input range. RNGA is used to select the range for the next

conversion on V1 and V2, RNGB is used to select the Range for

the next conversion on V3 and V4 and RNGC is used to select

the range for V5 and V6. When the RNGX is 1 the range on the

corresponding Analog input pair is ± 2 x VREF. When the

RNGX bit is 0 the range on the corresponding Analog Input

pair is ± 4 x VREF.

The REFEN pin is used to disable the internal reference,

allowing the user to supply an external reference to the

AD7658/AD7657/AD7656. When a 0 is written to this bit the

on-chip reference is disabled. When a 1 is written to this bit the

on-chip reference is enabled.

The REF BUF bit is used to disable the internal reference

buffers. When this bit is 1 the internal reference buffers are

disabled.

After a RESET occurs on the AD7658/AD7657/AD7656 the

Control register will contain all zeros.

Table 8.Control Register

D15

D14

D13

D12

D11

D10

D9

D8

VC

VB

VA

RNGC

RNGB

RNGA

REFEN

REFBUF

The CONVSTA signal is used to initiate a simultaneous

conversion on the combination of channels selected via the

Control register. The CONVSTB and CONVSTC signals can be

tied low when operating in software mode, H/S SEL = 1. The

number of read pulses required will depend on the number of

ADCs selected in the Control register and also whether

operating in word or BYTE mode. The conversion results will

be output in ascending order.

During the write operation the Data Bus bits DB15 to DB8 are

bidirectional and become inputs to the Control register when

RD is a logic high, CS and WR are logic low. The logic state on

DB15 through DB8 is latched into the Control register when

WR goes logic high.

t12

DATA

DB15-DB8

+5

94

t13

t14

t15

t16

Figure 8. Parallel Interface – Write cycle for Word Mode . (W/B= 0)

Changing the Analog Input Range(H/S SEL=0)

The AD7658/AD7657/AD7656 RANGE pin allows the user to

select either ± 2 x VREF or ± 4 x VREF as the analog input

range for the six Analog Inputs. When the H/S SEL pin is low

the logic state of the RANGE pin is sampled on the falling edge

of the BUSY signal to determine the range for the next

simultaneous conversion. When the RANGE pin is a logic high

at the falling edge of the BUSY signal the range for the next