ST25R3911B datasheet(74/116 Pages) STMICROELECTRONICS

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1.3.27

FIFO status register 1

Address: 1Ah

Type: R

Table 53. FIFO status register 1

Bit

Name

Default

Function

Comments(1)

fifo_b6 -

Number of bytes (binary coded) in the FIFO which were not read out

Valid range is from 0 (000 0000b) to 96

(110 0000b)

fifo_b5 -

fifo_b4 -

fifo_b3 -

fifo_b2 -

fifo_b1 -

fifo_b0 -

1. At power-up and after set default command content of this register is set to 0.

1.3.28

FIFO status register 2

Address: 1Bh

Type: R

Table 54. FIFO status register 2

Bit Name Default

Function

Comments(1)(2)(3)

fifo_unf -

1: FIFO underflow

Set when more bytes then actual content of FIFO were read

fifo_ovr -

1: FIFO overflow

fifo_lb2 -

Number of bits in the last FIFO byte if it was not

complete (fifo_ncp=1)

The received bits are stored in the LSB part of the last byte in

the FIFO

fifo_lb1 -

fifo_lb0 -

np_lb

1: Parity bit is missing in last byte

This is a framing error

1. At power-up and after set default command content of this register is set to 0.

2. If FIFO is empty, the value of register FIFO status register 1 (0x1Ah) is 0x00, register bits fifo_ncp, fifo_lb2,

fifo_lb1 and fifo_lb0 in register block 0x1Bh are cleared.

3. Correct procedure for FIFO read is to read both FIFO status register 1 and FIFO status register 1 and then

read FIFO. Second register values need to be saved in MCU because bits fifo_ncp, fifo_lb<2:0>, and np_lb

are cleared automatically at readout.

ST25R3911B

Registers

DS11793 - Rev 6

page 74/116

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