ST25R3911B datasheet(21/116 Pages) STMICROELECTRONICS

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Figure 10. SPI communication: writing a single byte

/SS

SCLK

MOSI

Two leading bits

indicate Mode

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

Data is moved to

address <A5-A0>

Raising

edge

indicates

end of

Write Mode

Figure 11. SPI communication: writing multiple bytes

/SS raising edge

indicates end of

Write mode

Two leading 0s

indicate Write mode

SCLK falling edge

Data moved to

address <A5-A0>

0 0

/SS

SCLK

MOSI

SCLK falling edge

Data moved to

address <A5-A0> + 1

SCLK falling edge

Data moved to

address <A5-A0> + (n-1)

SCLK falling edge

Data moved to

address <A5-A0> + n

Reading data from addressable registers (Read mode)

After the SPI operation mode bits the address of register to be read has to be provided from the MSB to the LSB.

Then one or more data bytes are transferred to MISO output, always from the MSB to the LSB. As in case of the

write mode also the read mode supports auto-incrementing address.

MOSI is sampled at the falling edge of SCLK (like shown in the following diagrams), data to be read from the

ST25R3911B internal register is driven to MISO pin on rising edge of SCLK and is sampled by the master at the

falling edge of SCLK.

In case the register on defined address does not exist all 0 data is sent to MISO.

Figure 12 is an example for reading of single byte.

ST25R3911B

Application information

DS11793 - Rev 6

page 21/116

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