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Data Sheet

AD9986

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 21 of 37

Table 20. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

JESD204B or JESD204C COMPATIBLE SERDES DATA

LANES AND CONTROL SIGNALS2

L18, L17

SERDIN0+, SERDIN0−

Input

JRx Lane 0 Inputs, Data True/Complement.

N18, N17

SERDIN1+, SERDIN1−

Input

JRx Lane 1 Inputs, Data True/Complement.

R18, R17

SERDIN2+, SERDIN2−

Input

JRx Lane 2 Inputs, Data True/Complement.

U18, U17

SERDIN3+, SERDIN3−

Input

JRx Lane 3 Inputs, Data True/Complement.

M15, M14

SERDIN4+, SERDIN4−

Input

JRx Lane 4 Inputs, Data True/Complement.

V15, V14

SERDIN5+, SERDIN5−

Input

JRx Lane 5 Inputs, Data True/Complement.

T15, T14

SERDIN6+, SERDIN6−

Input

JRx Lane 6 Inputs, Data True/Complement.

P15, P14

SERDIN7+, SERDIN7−

Input

JRx Lane 7 Inputs, Data True/Complement.

U13, V13

SYNC0OUTB+,

SYNC0OUTB−

Output

JRx Link 0 Synchronization Outputs for JESD204B interface.

These pins are LVDS or CMOS configurable. These pins can

also provide differential 100 Ω output impedance in LVDS

mode.

U12, V12

SYNC1OUTB+,

SYNC1OUTB−

Output

JRx Link 1 Synchronization Outputs for JESD204B interface

or CMOS Input for Transmit Fast Frequency Hopping (FFH)

via GPIOx pins. For sync output function, these pins are LVDS

or CMOS output configurable and can provide differential 100

Ω output impedance in LVDS mode.

A15, A14

SERDOUT0+,

SERDOUT0−

Output

JTx Lane 0 Outputs, Data True/Complement.

C15, C14

SERDOUT1+,

SERDOUT1−

Output

JTx Lane 1 Outputs, Data True/Complement.

E15, E14

SERDOUT2+,

SERDOUT2−

Output

JTx Lane 2 Outputs, Data True/Complement.

G15, G14

SERDOUT3+,

SERDOUT3−

Output

JTx Lane 3 Outputs, Data True/Complement.

H18, H17

SERDOUT4+,

SERDOUT4−

Output

JTx Lane 4 Outputs, Data True/Complement.

F18, F17

SERDOUT5+,

SERDOUT5−

Output

JTx Lane 5 Outputs, Data True/Complement.

D18, D17

SERDOUT6+,

SERDOUT6−

Output

JTx Lane 6 Outputs, Data True/Complement.

B18, B17

SERDOUT7+,

SERDOUT7−

Output

JTx Lane 7 Outputs, Data True/Complement.

B13, A13

SYNC0INB+, SYNC0INB− Input

JTx Link 0 Synchronization Inputs for JESD204B interface.

These pins are LVDS or CMOS configurable and have

selectable internal 100 Ω input impedance for LVDS operation.

B12, A12

SYNC1INB+, SYNC1INB− Input

JTx Link 1 Synchronization Inputs for JESD204B interface or

CMOS Inputs for Receive FFH via GPIOx pins. These pins are

LVDS or CMOS configurable and have selectable internal 100

Ω input impedance for LVDS operation.

T4, T3

SYSREFP, SYSREFN

Input

Active High JESD204B/C System Reference Inputs. These

pins are configurable for differential current mode logic (CML),

PECL, and LVDS with internal 100 Ω termination or single-

ended CMOS.

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