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ADIN1100BCPZ-R7 数据表(PDF) 40 Page - Analog Devices |
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ADIN1100BCPZ-R7 数据表(HTML) 40 Page - Analog Devices |
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40 / 78 page  Data Sheet ADIN1100 ETHERNET CLAUSE 22 REGISTER DETAILS analog.com Rev. 0 | 40 of 78 Table 35. Bit Descriptions for MI_STATUS Bits Bit Name Description Reset Access 14 MI_FD100_SPRT Full Duplex 100BASE-X Ability. The 100BASE-X full duplex ability bit always reads as 0 to indicate that the PHY does not support this technology. 0x0 R 13 MI_HD100_SPRT Half-Duplex 100BASE-X Ability. The 100BASE-X half-duplex ability bit always reads as 0 to indicate that the PHY does not support this technology. 0x0 R 12 MI_FD10_SPRT Full Duplex 10 Mbps Ability. The 10 Mbps full duplex ability bit indicates that the PHY supports this technology. 0x1 R 11 MI_HD10_SPRT Half-Duplex 10 Mbps Ability. The 10 Mbps half-duplex ability bit always reads as 0 to indicate that the PHY does not support this technology. 0x0 R 10 MI_FD_T2_SPRT Full Duplex 100BASE-T2 Ability. The 100BASE-T2 full duplex ability bit always reads as 0 to indicate that the PHY does not support this technology. 0x0 R 9 MI_HD_T2_SPRT Half-Duplex 100BASE-T2- Ability. The 100BASE-T2 half-duplex ability bit always reads as 0 to indicate that the PHY does not support this technology. 0x0 R 8 MI_EXT_STAT_SPRT Extended Status Support. The extended status support bit always reads as 0 to indicate that the PHY does not provide extended status information in Register 0xF. 0x0 R 7 MI_UNIDIR_ABLE Unidirectional Ability. The unidirectional ability bit always reads as 0 to indicate that the PHY can only transmit data from the MII when it has determined that a valid link has been established. 0x0 R 6 MI_MF_PREAM_SUP_ABLE Management Preamble Suppression Ability. The management frame preamble suppression ability bit always reads as 0 to indicate that the PHY is not able to receive management frames that are not preceded by the preamble pattern. 0x0 R 5 MI_AN_COMPLETE Autonegotiation Complete. The autonegotiation complete bit indicates that the autonegotiation process has been completed and the PHY link is up. Mirrors AN_COMPLETE. 0x0 R 4 MI_REM_FLT Remote Fault. The remote fault bit always reads as 0 because the PHY has no provision for remote fault detection. 0x0 R LH 3 MI_AN_ABLE Autonegotiation Ability. The autonegotiation ability bit always reads as 1 indicating that the PHY has the ability to perform autonegotiation. Mirrors AN_ABLE. 0x1 R 2 MI_LINK_STAT_LAT Link Status. The link status bit uses a latch low functionality as described in IEEE Standard 802.3 Subclause 45.2.7.20.5. If the link status value is fail, this bit clears and remains cleared until the latching is cleared when the bit is read. Mirrors 7.513.2 (AN_LINK_STATUS). 0x0 R LL 1 MI_JABBER_DET MII Jabber Detect. The jabber detect bit always reads as 0 because the 10BASE-T1L PHY does not incorporate a jabber detect function. 0x0 R LH 0 MI_EXT_CAPABLE MII Extended Capability. The extended capability bit always reads as 1, indicating that the PHY provides an extended set of capabilities that can be accessed through the extended register set. The extended register set consists of all of the management registers except 0x0, 0x1, and 0xF. 0x1 R PHY IDENTIFIER 1 REGISTER Address: 0x2, Reset: 0x0283, Name: MI_PHY_ID1 The PHY Identifier 1 address allows 16 bits of the OUI to be observed. Table 36. Bit Descriptions for MI_PHY_ID1 Bits Bit Name Description Reset Access [15:0] MI_PHY_ID1 The PHY Identifier 1 address allows 16 bits of the OUI to be observed. 0x283 R PHY IDENTIFIER 2 REGISTER Address: 0x3, Reset: 0xBC81, Name: MI_PHY_ID2 The PHY Identifier 2 address allows six bits of the OUI, and the model and revision number to be observed. Table 37. Bit Descriptions for MI_PHY_ID2 Bits Bit Name Description Reset Access [15:10] MI_PHY_ID2_OUI OUI, Bits[7:2]. 0x2F R |
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