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ADIN1100BCPZ-R7 数据表(PDF) 72 Page - Analog Devices |
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ADIN1100BCPZ-R7 数据表(HTML) 72 Page - Analog Devices |
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72 / 78 page  Data Sheet ADIN1100 ETHERNET CLAUSE 45 REGISTER DETAILS analog.com Rev. 0 | 72 of 78 This register is a latched copy of the oversized frame error counter register. This register is a count of receiver frames with a length greater than 1522 bytes. When the receive error counter (RX_ERR_CNT) is read, the oversized frame counter register is latched, which ensures that the oversized error count and the receive frame count are synchronized. Table 123. Bit Descriptions for FC_OSZ_CNT Bits Bit Name Description Reset Access [15:0] FC_OSZ_CNT Latched Copy of the Oversized Frame Error Counter. 0x0 R FRAME CHECKER UNDERSIZED FRAME COUNT REGISTER Device Address: 0x1F; Register Address: 0x800F, Reset: 0x0000, Name: FC_USZ_CNT This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes. When the receive error counter (RX_ERR_CNT) is read, the undersized frame error counter is latched, which ensures that the undersized frame error count and the receive frame count are synchronized. Table 124. Bit Descriptions for FC_USZ_CNT Bits Bit Name Description Reset Access [15:0] FC_USZ_CNT Latched Copy of the Undersized Frame Error Counter. 0x0 R FRAME CHECKER ODD NIBBLE FRAME COUNT REGISTER Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of frames in the frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd nibble frame count and the receive frame count are synchronized. Table 125. Bit Descriptions for FC_ODD_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_CNT Latched Copy of the Odd Nibble Counter. 0x0 R FRAME CHECKER ODD PREAMBLE PACKET COUNT REGISTER Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which ensures that the odd preamble packet count and the receive frame count are synchronized. Table 126. Bit Descriptions for FC_ODD_PRE_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_PRE_CNT Latched Copy of the Odd Preamble Packet Counter. 0x0 R FRAME CHECKER FALSE CARRIER COUNT REGISTER Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT This register is a latched copy of the false carrier events counter register. This register is a count of the number of times the bad SSD state is entered. When the receive error counter (RX_CNT_ERR) is read, the false carrier events counter register is latched, which ensures that the false carrier events count and the receive frame count are synchronized. Table 127. Bit Descriptions for FC_FALSE_CARRIER_CNT Bits Bit Name Description Reset Access [15:0] FC_FALSE_CARRIER_CNT Latched Copy of the False Carrier Events Counter. 0x0 R |
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