Enhanced Product

ADMV8913-EP

Rev. 0 | Page 7 of 23

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

30

1

5

4

3

2

GND

GND

GND

RF1

GND

GND

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED

TO THE RF AND DC GROUND.

GND

GND

RF2

GND

20

16

17

18

19

29

28

27

26

25

24

23

22

21

6

7

8

9

10

11

12

13

14

15

ADMV8913-EP

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4, 5, 13, 16, 17, 19, 20

GND

Ground. Connect the GND pins to the RF and dc ground.

3

RF1

RF Pin 1. RF1 is dc-coupled and matched to 50 Ω. Do not apply an external voltage to RF1.

6

RST

Chip Reset. 3.3 V logic. Active low. The RST pin is internally pulled high with a 260 kΩ resistor.

7

SCLK

SPI Clock. 3.3 V logic. The SCLK pin is internally pulled low with a 260 kΩ resistor.

8

CS

SPI Chip Select. 3.3 V logic. Active low. The CS pin is internally pulled low with a 260 kΩ resistor. In

parallel mode, the CS pin can be toggled high to latch in logic data synchronously or held high

for asynchronous logic update.

9

SDI

SPI Data Input. 3.3 V logic. The SDI pin is internally pulled low with a 260 kΩ resistor.

10

SDO

SPI Data Output. 3.3 V logic. The SDO pin is internally pulled low with a 260 kΩ resistor.

11

SFL

SPI Fast Latch Enable. 3.3 V logic. Set SFL high to enable fast latching of filter states on each

rising edge of CS. While SFL is in this mode, the SCLK, SDO, and SDI pins are not active. The SFL

pin is internally pulled low with a 260 kΩ resistor.

12

VDD1

2.5 V Power Supply Pin. Place 47 µF, 0.1 µF, and 100 pF decoupling capacitors close to VDD1. By

default, the 2.5 V voltage is generated by an on-chip LDO regulator. To provide voltage to

VDD1 ground the LDO_EN pin to disable the on-chip LDO regulator. Do not apply an external

voltage to VDD1 when the LDO regulator is enabled.

14

VDD2

3.3 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to VDD2.

15

VSS1

–2.5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to VSS1.

18

RF2

RF Pin 2. RF2 is dc-coupled and matched to 50 Ω. Do not apply an external voltage to RF2.

21

LDO_EN

LDO Regulator Enable Input. 3.3 V logic. The LDO_EN pin is internally pulled high with a 260 kΩ

resistor. Ground LDO_EN to disable the on-chip LDO regulator. Leave LDO_EN floating for logic

high to enable the on-chip LDO regulator (recommended configuration).

22

LPF_B0

LPF Bit 0. 3.3 V logic. The LPF_B0 pin is internally pulled low with a 260 kΩ resistor.

23

LPF_B1

LPF Bit 1. 3.3 V logic. The LPF_B1 pin is internally pulled low with a 260 kΩ resistor.

24

LPF_B2

LPF Bit 2. 3.3 V logic. The LPF_B2 pin is internally pulled low with a 260 kΩ resistor.

25

LPF_B3

LPF Bit 3. 3.3 V logic. The LPF_B3 pin is internally pulled low with a 260 kΩ resistor.

26

HPF_B0

HPF Bit 0. 3.3 V logic. The HPF_B0 pin is internally pulled low with a 260 kΩ resistor.