ADMV8913-EP

Enhanced Product

Rev. 0 | Page 12 of 23

MODE SELECTION

The ADMV8913-EP has three modes of operation: parallel, SPI

write, and SPI fast latch. Parallel mode is used to bypass the SPI

to allow the filters to be programmed directly using the

HPF_B3 to HPF_B0 and LPF_B3 to LPF_B0 logic inputs. To select

parallel mode, set the PS pin low. Otherwise, set the PS pin high

to enable the SPI for use with SPI write or SPI fast latch mode.

SPI write mode is the normal operating mode, whereas SPI fast

latch mode is used to sequence through the on-chip lookup

table (LUT) using the internal state machine. To select SPI

write mode, set the PS pin high and the SFL pin low. For

operation in SPI fast latch mode, program the on-chip LUT and

fast latch parameters with the PS pin high and the SFL pin low,

and then bring the SFL pin high to enter this mode. Figure 19

shows a simplified representation of the parallel logic and SPI

with the register map and internal state machine.

REGISTER MAP

HPF LOGIC

PARAMETERS

AND LUT

SCLK

SDI

CS

SFL

SDO

FILTERS

WR

INTERNAL

STATE MACHINE

LPF LOGIC

START LOCATION

•••

STOP LOCATION

Figure 19. Simplified Interface and Logic Diagram

PARALLEL MODE

Parallel mode uses the HPF_B3 to HPF_B0 and LPF_B3 to

LPF_B0 logic inputs to set the state of the HPF and the LPF.

While in parallel mode, there are two types of logic operations,

synchronous and asynchronous. For synchronous operation,

the state on the HPF_B3 to HPF_B0 and LPF_B3 to LPF_B0

logic inputs is only latched to the HPF and LPF on the rising

edge of the CS pin. For asynchronous operation, the CS pin is

held high and then any change to the HPF_B3 to HPF_B0 and

LPF_B3 to LPF_B0 logic inputs asynchronously propagates to

the HPF and LPF.

SPI WRITE MODE

SPI write mode uses Register 0x020 (WR) to set the state of the

HPF and the LPF that correspond to the HPF_WR and LPF_WR

bit fields, respectively. See the Register Details section for a

visual representation of Register 0x020 and its corresponding

bit fields.

FILTER SETTINGS

The HPF and LPF each contain 16 states (4 bits). A value of zero

of the filter to its highest possible frequency.

SPI FAST LATCH MODE

The ADMV8913-EP has a 128 state LUT and an internal state

machine that is useful for quickly changing filter states in SPI

fast latch mode. When the SFL pin is high, SPI fast latch mode

enables, and the internal state machine sequences on each

rising edge of the CS pin.

The LUT has 128 indices, LUT0 through LUT127 (Register 0x100

through Register 0x17F). Each index consists of the same type

of parameters as those of SPI write mode.

The functionality of the internal state machine is such that on

each rising edge of the CS pin, the internal state machine sequences

a pointer based on the programmed direction. The internal

state machine has the following parameters:

•

FAST_LATCH_STOP (Register 0x011)

•

FAST_LATCH_START (Register 0x012)

•

FAST_LATCH_DIRECTION (Register 0x013)

•

FAST_LATCH_STATE (Register 0x014)

The FAST_LATCH_STATE is the next LUT indices that

is selected on the next rising edge of the CS pin. The

FAST_LATCH_STATE is considered the internal pointer

location.

When the FAST_LATCH_DIRECTION bit is set to zero,

the sequencing direction is incremental. When the

FAST_LATCH_DIRECTION bit is set to one, the sequencing

direction is decremental.

The FAST_LATCH_START and FAST_LATCH_STOP bits set

the start and stop location, respectively. For incremental direction,

the internal state machine sequences from the start location to

the stop location and then rolls over to the start location. For

the decremental direction, the sequence is from the stop location

to the start location and then rolls over to the stop location.

The FAST_LATCH_STATE internal pointer is set to the values

stored in FAST_LATCH_START for the incremental direction.

For the decremental direction, the internal pointer is to the

values stored in FAST_LATCH_STOP. For this transaction to

occur, one rising edge of the CS pin is necessary. By nature,

this occurs during a SPI transaction in SPI write mode.

However, when exiting SPI fast latch mode (SFL pin brought low),

toggle the CS pin low then high or perform a SPI transaction so

that the FAST_LATCH_STATE refreshes to either the start or

stop location accordingly.