Enhanced Product

ADMV8913-EP

Rev. 0 | Page 13 of 23

SPI STREAMING

In general, there are two types of SPI streaming transactions,

Endian register ascending order and Endian register

descending order. The ADMV8913-EP supports only the

ascending order. To enable SPI streaming with Endian register

ascending order, program Register 0x00 to a value of 0x3C.

For SPI streaming to the LUT, Register 0x100 to Register 0x17F

(recommended), the transaction points to Register 0x100 and

streams out 128 bytes of data. The transaction is 1040 bits in

total (R/W bit + 15 bits address + 1024 bits data).

CHIP RESET

There are two methods that can reset the ADMV8913-EP registers

to their default power-on state, a hard reset and a soft reset. The

hard reset utilizes the RST pin, and the soft reset utilizes

Register 0x000.

To perform a hard reset, momentarily bring the RST pin low

and then high. See Figure 2 for the minimum required duration

time for the RST pin to be low.

To perform a soft reset, program Register 0x000 to a value of 0x81.

This action sets the SOFTRESET and SOFTRESET_ bits high to

initiate the reset. The SOFTRESET and SOFTRESET_ bits are

self resetting once the reset operation completes.

Regardless of the reset method used, it is recommended to

perform the following after the chip resets:

•

Program Register 0x000 to 0x3C to enable the SDO pin

and allow SPI streaming with Endian ascending order.

•

Read back all registers on the chip.