Enhanced Product

ADMV8913-EP

Rev. 0 | Page 11 of 23

THEORY OF OPERATION

CHIP ARCHITECTURE

The ADMV8913-EP is a combination tunable HPF and tunable

LPF that can achieve pass-band responses in the X band frequency

range. Figure 1 is a conceptual block diagram of the ADMV8913-EP.

TUNABLE HIGH-PASS FILTER

Figure 16 shows a simplified schematic of the HPF, which is

Capacitor C1 to Capacitor C4. These tunable capacitors are

constructed with 4-bit digital capacitor arrays, providing

16 distinct values. The step size of these tunable capacitors

is adjusted so that each digital binary code increment creates

RFC shown in Figure 16 is the internal connection of the HPF

and LPF.

L1

L2

C3

L3

C4

RF1

RFC

C2

C1

Figure 16. HPF Simplified Schematic

TUNABLE LOW-PASS FILTER

Figure 17 shows a simplified schematic of the LPF, which is

Capacitor C1 to Capacitor C4. These tunable capacitors are

constructed with 4-bit digital capacitor arrays, providing

16 distinct values. The step size of these tunable capacitors is

adjusted so that each digital binary code increment creates

RFC shown in Figure 17 is the internal connection of the HPF

and LPF.

C1

C2

L3

C3

RFC

RF2

L2

L1

C4

Figure 17. LPF Simplified Schematic

RF CONNECTIONS

The RF1 and RF2 pins of the ADMV8913-EP are dc-coupled to

on-chip ESD protection diodes. If a dc voltage is present on the

RF1 and RF2 pins from other components within the system, it

is recommended to place dc blocking capacitors in series with these

pins. The dc blocking capacitors must be selected based on the

operating frequency of the filter. Generally, a value greater than

100 pF is sufficient to minimize insertion loss at the lower

operating frequencies. At higher operating frequencies, it may

be necessary to consider the parasitic elements of the selected

capacitor. Figure 18 shows a general model of a capacitor with the

of most concern given that its impedance can become dominant at

frequencies higher than 10 GHz. The other parasitic elements,

consideration but are shown here for completeness.

C

Figure 18. General Model of a Capacitor

SPI CONFIGURATION

The SPI of the ADMV8913-EP allows configuration of the

device for specific functions or operations via the 5-pin SPI

port. This interface provides users with added flexibility and

customization. The SPI consists of five control lines: SFL, SCLK,

SDI, SDO, and CS. For normal SPI operations, keep the SFL pin

low.

The SPI protocol consists of an R/W bit followed by 15 register

address bits and 8 data bits. The address field and data field are

organized MSB first and end with the LSB.

Set the MSB to 0 for a write operation, and set the MSB to 1 for a

read operation. The write cycle must be sampled on the rising

edge of SCLK. The 24 bits of the serial write address and data are

shifted in on the SDI control line, MSB to LSB. The ADMV8913-

EP input logic level for the write cycle supports a 3.3 V interface.

For a read cycle, the R/W bit and the 15 register address bits

shift in on the rising edge of SCLK on the SDI control line. Then,

8 bits of serial read data shift out on the SDO control line, MSB

first, on the falling edge of SCLK. The output logic level for a

read cycle is 3.3 V. The output drivers of the SDO are enabled

after the last rising edge of SCLK of the instruction cycle and

remain active until the end of the read cycle. In a read operation,

when CS is deasserted, SDO returns to high impedance until the

next read transaction. CS is active low and must be deasserted

at the end of the write or read sequence.

An active low input on CS starts and gates a communication

cycle. The CS pin allows more than one device to be used on

the same serial communications lines. The SDO pin goes to a

high impedance state when the CS input is high. During the

communication cycle, the chip select must stay low. The SPI

communications protocol follows the Analog Devices SPI

standard. For more information, see the ADI-SPI Serial

Control Interface Standard (Rev 1.0).