Data Sheet

ADPA1106

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. 0 | 5 of 19

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 8, 9, 16, 17, 22, 24,

25, 32

GND

Ground. The GND pins must be connected to RF and dc ground. See Figure 6 for the interface schematic.

2

VREF

the application of a dc bias voltage through an external series resistor.

4, 5, 7, 12, 13, 14, 18,

20, 21, 23, 26, 27, 29, 30

NIC

Not Internally Connected. The NIC pins are not internally connected. However, all data shown is measured with the NIC pins

connected to RF and dc ground externally.

6

RFIN

RF Input. The RFIN pin is ac-coupled and is matched to 50 Ω. See Figure 3 for the interface schematic.

10

VGG1

Gate Control, First Stage Gate Bias. See Figure 3 for the interface schematic.

11

VGG2

Gate Control, Second Stage Gate Bias. See Figure 4 for the interface schematic.

15

VDET

19

RFOUT

RF Output. The RFOUT pin is ac-coupled and is matched to 50 Ω. See Figure 4 for the interface schematic.

28

VDD2

Amplifier Power Supply Voltage, Second Stage Drain Bias. See Figure 4 for the interface schematic.

31

VDD1

Amplifier Power Supply Voltage, First Stage Drain Bias. See Figure 3 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and dc ground.

INTERFACE SCHEMATICS

Figure 3. RFIN, VGG1, and VDD1 Interface Schematic

Figure 4. RFOUT, VGG2, VDD2, and VDET Interface Schematic

Figure 5. VREF Interface Schematic

Figure 6. GND Interface Schematic