Data Sheet

ADPA1106

APPLICATIONS INFORMATION

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Rev. 0 | 15 of 19

BASIC CONNECTIONS

The basic connections for operating the ADPA1106 are shown in

Figure 52. Apply a power supply voltage between 45 V and 55 V

(nominally 50 V) to the VDD1 and VDD2 pins (Pin 31 and Pin 28,

respectively). Decouple each pin with the capacitor values shown

in Figure 52. Place 3.9 Ω resistors in series with the two 390 pF

power supply decoupling capacitors connected to VDD2 and VDD1.

In addition, place a 3.9 Ω resistor in series with a 1000 pF capacitor

connected to VDD1. Tie together the two gate voltage pins, VGG1

and VGG2, and drive these pins as shown in Figure 52. Pin 4,

Pin 5, Pin 7, Pin 12, Pin 13, Pin 18, Pin 22, Pin 23, Pin 26,

Pin 27, Pin 29, and Pin 30 are designated as not internally connect-

ed (NIC) pins. Although these pins are not internally connected, the

NIC pins were all connected to ground during the characterization

of the device.

The decoupling capacitors on the VDD1, VDD2, VGG1, and VGG2

lines represent the configuration that was used to characterize the

ADPA1106. It is possible to reduce the number of capacitors on

the VGG1 and VGG2 lines. General guidance is to first remove

or combine the largest value capacitors that are farthest from the

device. All of the capacitors and resistors connected to the VDD1

and VDD2 pins in Figure 52 must be used.

External bias is provided to the on-chip RF detection circuit via two

100 kΩ resistors that are pulled up to 5 V, which results in a current

draw of approximately 100 μA. An operational amplifier configured

as a differential amplifier can be used to subtract VDET from VREF

to yield a temperature compensated voltage that is proportional to

Because the ADPA1106 cannot support continuous operation, the

device must be operated in pulsed mode by pulsing either the gate

voltage or the drain voltage.

while the gate voltage is pulsed between −4 V (off) and approxi-

mately −2.3 V (on). The exact on level can be adjusted to achieve

gate voltage is held at a fixed negative level between 0 V and

−4 V. Because high currents and voltages are being switched on

and off, a metal-oxide semiconductor field effect transistor (MOS-

FET) and a MOSFET switch driver are required in the circuit. Large

capacitors are also required, which act as local reservoirs of charge

and help provide the drain current required by the ADPA1106 while

maintaining a steady drain voltage during the on time of the pulse.

The ADPA1106-EVALZ evaluation board package includes a plugin

pulser board that contains the required circuitry to implement drain

pulsed mode. See the ADPA1106-EVALZ for more information.